M80C286 datasheet(49/60 Pages) INTEL

Part #	M80C286

Description	HIGH PERFORMANCE CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION

PDF	60 Pages

Scroll/Zoom	100%

Manufacturer	INTEL [Intel Corporation]

Direct Link	http://www.intel.com

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49 / 60 page

M80C286

WAVEFORMS (Continued)

M80C286 PEREQPEACK TIMING FOR ONE TRANSFER ONLY

NOTES

271103 – 48

1 PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence

The first bus operation will be either a memory read at operand address or IO read at port address OOFA(H)

2 To prevent a second processor extension data operand transfer the worst case maximum time (Shown above) is

3c j b12a2max b mmin

The actual

configuration dependent

maximum time is

3c j b12a2max b mmin a

Ac2c j

A is the number of extra TC states added to either the first or second bus operation of the processor extension data

operand transfer sequence

INITIAL M80C286 PIN STATE DURING RESET

NOTES

271103 – 49

1 Setup time for RESET

u may be violated with the consideration that w1 of the processor clock may begin one

system CLK period later

2 Setup and hold times for RESET

v must be met for proper operation but RESET v may occur during w1or w2

3 The data bus is only guaranteed to be in 3-state OFF at the time shown

M80C286 Datasheet(PDF) 49 Page - Intel Corporation