M80C286 datasheet(39/60 Pages) INTEL

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M80C286

Table 18 Pin Description

(Continued)

Symbol

Type

Name and Function

NMI

NON-MASKABLE INTERRUPT REQUEST

interrupts the M80C286 with an

internally supplied vector value of 2 No interrupt acknowledge cycles are

performed The interrupt enable bit in the M80C286 flag word does not affect

this input The NMI input is active HIGH may be asynchronous to the system

clock and is edge triggered after internal synchronization For proper

recognition the input must have been previously LOW for at least four system

clock cycles and remain HIGH for at least four system clock cycles

PEREQ

PROCESSOR EXTENSION OPERAND REQUEST AND ACKNOWLEDGE

PEACK

extend the memory management and protection capabilities of the M80C286

to processor extensions The PEREQ input requests the M80C286 to perform

a data operand transfer for a processor extension The PEACK output signals

the processor extension when the requested operand is being transferred

PEREQ is active HIGH and floats to 3-state OFF during bus hold

acknowledge PEACK may be asynchronous to the system clock PEACK is

active LOW

BUSY

PROCESSOR EXTENSION BUSY AND ERROR

indicate the operating

ERROR

condition of a processor extension to the M80C286 An active BUSY input

stops M80C286 program execution on WAIT and some ESC instructions until

BUSY becomes inactive (HIGH) The M80C286 may be interrupted while

waiting for BUSY to become inactive An active ERROR input causes the

M80C286 to perform a processor extension interrupt when executing WAIT or

some ESC instructions These inputs are active LOW and may be

asynchronous to the system clock These inputs have internal pull-up

resistors

RESET

SYSTEM RESET

clears the internal logic of the M80C286 and is active HIGH

The M80C286 may be reinitialized at any time with a LOW to HIGH transition

on RESET which remains active for more than 16 system clock cycles During

RESET active the output pins of the M80C286 enter the state shown below

M80C286 Pin State During Reset

Pin Value

Pin Names

1 (HIGH)

S0 S1 PEACK A23 – A0 BHE LOCK

0 (LOW)

MIO CODINTA HLDA (Note 1)

3-state OFF

D15–D0

Operation of the M80C286 begins after a HIGH to LOW transition on RESET

The HIGH to LOW transition of RESET must be synchronous to the system

clock Approximately 38 CLK cycles from the trailing edge of RESET are

required by the M80C286 for internal initialization before the first bus cycle to

fetch code from the power-on execution address occurs

A LOW to HIGH transition of RESET synchronous to the system clock will

end a processor cycle at the second HIGH to LOW transition of the system

clock The LOW to HIGH transition of RESET may be asynchronous to the

system clock however in this case it cannot be predetermined which phase

of the processor clock will occur during the next system clock period

Synchronous LOW to HIGH transitions of RESET are required only for

systems where the processor clock must be phase synchronous to another

clock

VSS

SYSTEM GROUND

0 Volts

VCC

SYSTEM POWER a

5 Volt Power Supply

CAP

SUBSTRATE FILTER CAPACITOR

a 0047 mF g 20% 12V capacitor can

be connected between this pin and ground for compatibility with the HMOS

M80286 For systems using only an M80C286 this pin can be left floating

See bus hold circuitry section

NOTE

1 HLDA is only Low if HOLD is inactive (Low)

M80C286 Datasheet(PDF) 39 Page - Intel Corporation

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