M80C286 datasheet(28/60 Pages) INTEL

28 / 60 page

M80C286

In real address mode the prefetcher may fetch up to

6 bytes beyond the last control transfer or HLT in-

struction in a code segment

In protected mode the prefetcher will never cause a

segment overrun exception The prefetcher stops at

the last physical memory word of the code segment

Exception 13 will occur if the program attempts to

execute beyond the last full instruction in the code

segment

If the last byte of a code segment appears on an

even physical memory address the prefetcher will

read the next physical byte of memory (perform a

word code fetch) The value of this byte is ignored

and any attempt to execute it causes exception 13

271103 – 27

NOTES

1 Status lines are not driven by M80C286 yet remain high due to internal pullup resistors during HOLD state See

section on bus hold circuitry

2 Address MIO and CODINTA may start floating during any TC depending on when internal M80C286 bus arbiter

decides to release bus to external HOLD The float starts in w2ofTC See section on bus hold circuitry

3 BHE and LOCK may start floating after the end of any TC depending on when internal M80C286 bus arbiter decides

to release bus to external HOLD The float starts in w1ofTC See section on bus hold circuitry

4 The minimum HOLD to HLDA time is shown Maximum is one TH longer

5 The earliest HOLD time is shown It will always allow a subsequent memory cycle if pending is shown

6 The minimum HOLD to HLDA time is shown Maximum is a function of the instruction type of bus cycle and other

machine state (ie Interrupts Waits Lock etc)

7 Asynchronous ready allows termination of the cycle Synchronous ready does not signal ready in this example Syn-

chronous ready state is ignored after ready is signaled via the asynchronous input

Figure 29 MULTIBUS Write Terminated by Asynchronous Ready with Bus Hold

M80C286 Datasheet(PDF) 28 Page - Intel Corporation