M80C286 datasheet(38/60 Pages) INTEL

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M80C286

Table 18 Pin Description

(Continued)

Symbol

Type

Name and Function

BHE

BHE and A0 Encodings

(Continued)

BHE Value

A0 Value

Function

Word transfer

Transfer on upper half of data bus (D15–D8)

Byte transfer on lower half of data bus (D7–D0)

Will never occur

S1 S0

BUS CYCLE STATUS

indicates initiation of a bus cycle and along with MIO and COD

INTA defines the type of bus cycle The bus is in a Ts state whenever one or both are LOW

S1 and S0 are active LOW and float to 3-state OFF during bus hold acknowledge

M80C286 Bus Cycle Status Definition

CODINTA

MIO

Bus Cycle Initiated

0 (LOW)

Interrupt acknowledge

Will not occur

None not a status cycle

IF A1 e 1 then halt else shutdown

Memory data read

Memory data write

None not a status cycle

1 (HIGH)

Will not occur

IO read

IO write

None not a status cycle

Will not occur

Memory instruction read

Will not occur

None not a status cycle

MIO

MEMORY IO SELECT

distinguishes memory access from IO access If HIGH during Ts a

memory cycle or a haltshutdown cycle is in progress If LOW an IO cycle or an interrupt

acknowledge cycle is in progress MIO floats to 3-state OFF during bus hold

acknowledge

CODINTA

CODEINTERRUPT ACKNOWLEDGE

distinguishes instruction fetch cycles from memory

data read cycles Also distinguishes interrupt acknowledge cycles from IO cycles COD

INTA floats to 3-state OFF during bus hold acknowledge Its timing is the same as MIO

LOCK

BUS LOCK

indicates that other system bus masters are not to gain control of the system

bus for the current and the following bus cycle The LOCK signal may be activated explicitly

by the ‘‘LOCK’’ instruction prefix or automatically by M80C286 hardware during memory

XCHG instructions interrupt acknowledge or descriptor table access LOCK is active LOW

and floats to 3-state OFF during bus hold acknowledge

READY

BUS READY

terminates a bus cycle Bus cycles are extended without limit until terminated

by READY LOW READY is an active LOW synchronous input requiring setup and hold

times relative to the system clock be met for correct operation READY is ignored during

bus hold acknowledge

HOLD

BUS HOLD REQUEST AND HOLD ACKNOWLEDGE

control ownership of the M80C286

HLDA

local bus The HOLD input allows another local bus master to request control of the local

bus When control is granted the M80C286 will float its bus drivers to 3-state OFF and

then activate HLDA thus entering the bus hold acknowledge condition The local bus will

remain granted to the requesting master until HOLD becomes inactive which results in the

M80C286 deactivating HLDA and regaining control of the local bus This terminates the bus

hold acknowledge condition HOLD may be asynchronous to the system clock These

signals are active HIGH

INTR

INTERRUPT REQUEST

requests the M80C286 to suspend its current program execution

and service a pending external request Interrupt requests are masked whenever the

interrupt enable bit in the flag word is cleared When the M80C286 responds to an interrupt

request it performs two interrupt acknowledge bus cycles to read an 8-bit interrupt vector

that identifies the source of the interrupt To assure program interruption INTR must remain

active until the first interrupt acknowledge cycle is completed INTR is sampled at the

beginning of each processor cycle and must be active HIGH at least two processor cycles

before the current instruction ends in order to interrupt before the next instruction INTR is

level sensitive active HIGH and may be asynchronous to the system clock

See bus hold circuitry section

M80C286 Datasheet(PDF) 38 Page - Intel Corporation

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