M80C286 datasheet(22/60 Pages) INTEL

22 / 60 page

M80C286

Two bus signals A0 and BHE control transfers over

the lower and upper halves of the data bus Even

address byte transfers are indicated by A0 LOW and

BHE HIGH Odd address byte transfers are indicat-

ed by A0 HIGH and BHE LOW Both A0 and BHE are

LOW for even address word transfers

The IO address space contains 64K addresses in

both modes The IO space is accessible as either

bytes or words as is memory Byte wide peripheral

devices may be attached to either the upper or lower

byte of the data bus Byte-wide IO devices attached

to the upper data byte (D15–D8) are accessed with

odd IO addresses Devices on the lower data byte

are accessed with even IO addresses An interrupt

controller such as Intel’s 82C59A-2 must be con-

nected to the lower data byte (D7–D0) for proper

return of the interrupt vector

Bus Operation

The M80C286 uses a double frequency system

clock (CLK input) to control bus timing All signals on

the local bus are measured relative to the system

CLK input The CPU divides the system clock by 2 to

produce the internal processor clock which deter-

mines bus state Each processor clock is composed

of two system clock cycles named phase 1 and

phase 2

The M82C284 clock generator output

(PCLK) identifies the next phase of the processor

clock (See Figure 21)

271103 – 19

Figure 21 System and Processor

Clock Relationships

Six types of bus operations are supported memory

read memory write IO read IO write interrupt ac-

knowledge and haltshutdown Data can be trans-

ferred at a maximum rate of one word per two proc-

essor clock cycles

The M80C286 bus has three basic states idle (Ti)

send status (Ts) and perform command (Tc) The

M80C286 CPU also has a fourth local bus state

called hold (Th) Th indicates that the M80C286 has

surrendered control of the local bus to another bus

master in response to a HOLD request

Each bus state is one processor clock long Figure

22 shows the four M80C286 local bus states and

allowed transitions

271103 – 20

Figure 22 M80C286 Bus States

Bus States

The idle (Ti) state indicates that no data transfers

are in progress or requested The first active state

TS is signaled by status line S1 or S0 going LOW

and identifying phase 1 of the processor clock Dur-

ing TS the command encoding the address and

data (for a write operation) are available on the

M80C286 output pins The M82C288 bus controller

decodes the status signals and generates Multibus

compatible readwrite command and local trans-

ceiver control signals

After TS the perform command (TC) state is en-

tered Memory or IO devices respond to the bus

operation during TC either transferring read data to

the CPU or accepting write data TC states may be

repeated as often as necessary to assure sufficient

time for the memory or IO device to respond The

READY signal determines whether TC is repeated A

repeated TC state is called a wait state

During hold (Th) the M80C286 will float all address

data and status output pins enabling another bus

master to use the local bus The M80C286 HOLD

input signal is used to place the M80C286 into the

Th state The M80C286 HLDA output signal indi-

cates that the CPU has entered Th

Pipelined Addressing

The M80C286 uses a local bus interface with pipe-

lined timing to allow as much time as possible for

data access Pipelined timing allows a new bus oper-

ation to be initiated every two processor cycles

while allowing each individual bus operation to last

for three processor cycles

The timing of the address outputs is pipelined such

that the address of the next bus operation becomes

available during the current bus operation Or in oth-

er words the first clock of the next bus operation is

overlapped with the last clock of the current bus op-

eration Therefore address decode and routing logic

can operate in advance of the next bus operation

NOTE

See section on bus hold circuitry

M80C286 Datasheet(PDF) 22 Page - Intel Corporation

M80C286 Datasheet(HTML) 22 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL