M80C286 datasheet(35/60 Pages) INTEL

35 / 60 page

M80C286

271103 – 34

Figure 36 M80C286 System Configuration with Dual-Ported Memory

Figure 36 shows the addition of dual ported dynamic

memory between the MULTIBUS system bus and

the M80C286 local bus The dual port interface is

provided by the 8207 Dual Port DRAM Controller

The 8207 runs synchronously with the CPU to maxi-

mize throughput for local memory references It also

arbitrates between requests from the local and sys-

tem buses and performs functions such as refresh

initialization of RAM and readmodifywrite cycles

The 8207 combined with the 8206 Error Checking

and Correction memory controller provide for single

bit error correction The dual-ported memory can be

combined with a standard MULTIBUS system bus

interface to maximize performance and protection in

multiprocessor system configurations

Mechanical Data

The M80C286 pinout for both the Ceramic Quad

Flatpack CQFP and Pin Grid Array PGA packages

are shown in Figure 37 VCC and GND connections

must be made to mutiple VCC and VSS (GND) pins

Each VCC and VSS MUST be connected to the ap-

propriate voltage level The circuit board should in-

clude VCC and GND planes for power distribution

and all VCC pins must be connected to the appropri-

ate plane

Table 17 shows the pin assignments for both the

CQFP and PGA components

NOTE

Pins identified as ‘‘NC’’ should remain completely

unconnected

M80C286 Datasheet(PDF) 35 Page - Intel Corporation