M80C286 datasheet(25/60 Pages) INTEL

25 / 60 page

M80C286

NOTES

271103 – 23

1 SRDYEN is active low

2 If SRDYEN is high the state of SRDY will no affect READY

3 ARDYEN is active low

Figure 25 Synchronous and Asynchronous Ready

ARDY or ARDYEN must be HIGH at the end of TS

ARDY cannot be used to terminate bus cycle with no

wait states

Each ready input of the M82C284 has an enable pin

(SRDYEN and ARDYEN) to select whether the cur-

rent bus operation will be terminated by the synchro-

nous or asynchronous ready Either of the ready in-

puts may terminate a bus operation These enable

inputs are active low and have the same timing as

their respective ready inputs Address decode logic

usually selects whether the current bus operation

should be terminated by ARDY or SRDY

Data Bus Control

Figures 26 27 and 28 show how the DTR DEN

data bus and address signals operate for different

combinations of read write and idle bus operations

DTR goes active (LOW) for a read operation DTR

remains HIGH before during and between write op-

erations

The data bus is driven with write data during the

second phase of Ts The delay in write data timing

allows the read data drivers from a previous read

cycle sufficient time to enter 3-state OFF

before

the M80C286 CPU begins driving the local data bus

for write operations Write data will always remain

valid for one system clock past the last Tc to provide

sufficient hold time for Multibus or other similar

memory or IO systems During write-read or write-

idle sequences the data bus enters 3-state OFF

during the second phase of the processor cycle after

the last Tc In a write-write sequence the data bus

does not enter 3-state OFF between Tc and Ts

Bus Usage

The M80C286 local bus may be used for several

functions instruction data transfers data transfers

by other bus masters instruction fetching processor

extension data transfers interrupt acknowledge and

haltshutdown This section describes local bus ac-

tivities which have special signals or requirements

NOTE

See section on bus hold circuitry

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