M80C286 datasheet(48/60 Pages) INTEL

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M80C286

WAVEFORMS (Continued)

M80C286 ASYNCHRONOUS

INPUT SIGNAL TIMING

271103 – 45

NOTES

1 PCLK indicates which processor cycle phase will oc-

cur on the next CLK PCLK may not indicate the cor-

rect phase until the first bus cycle is performed

2 These inputs are asynchronous The setup and hold

times shown assure recognition for testing purposes

M80C286 RESET INPUT TIMING AND

SUBSEQUENT PROCESSOR CYCLE PHASE

271103 – 46

NOTE

1 When RESET meets the setup time shown the next

CLK will start or repeat w2 of a processor cycle

EXITING AND ENTERING HOLD

271103 – 47

NOTES

1 These signals may not be driven by the M80C286 during the time shown The worst case in terms of latest float time

is shown

2 The data bus will be driven as shown if the last cycle before TI in the diagram was a write TC

3 The M80C286 floats its status pins during TH External 20 KX resistors keep these signals high (see Table 16)

4 For HOLD request set up to HLDA refer to Figure 29

5 BHE and LOCK are driven at this time but will not become valid until TS

6 The data bus will remain in 3-state OFF if a read cycle is performed

M80C286 Datasheet(PDF) 48 Page - Intel Corporation