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R5F36CAMNFB Datasheet(PDF) 12 Page - Renesas Technology Corp |
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R5F36CAMNFB Datasheet(HTML) 12 Page - Renesas Technology Corp |
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12 / 100 page ![]() R01DS0034EJ0210 Rev.2.10 Page 12 of 96 Jul 31, 2012 M16C/6C Group 1. Overview Notes: 1. Contact the manufacturer of crystal/ceramic resonator regarding the oscillation characteristics. 2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi, SDAi, and SCLi can be selected as CMOS output pins or N-channel open drain output pins. (i = 0, 1, 3 to 5) Table 1.7 Pin Functions (2/3) Signal Name Pin Name I/O Power Supply Description Main clock input XIN I VCC1 I/O for the main clock oscillator. Connect a ceramic resonator or crystal between pins XIN and XOUT. (1) Input an external clock to XIN pin and leave XOUT pin open. Main clock output XOUT O VCC1 Sub clock input XCIN I VCC1 I/O for a sub clock oscillator. Connect a crystal between XCIN pin and XCOUT pin. (1) Input an external clock to XCIN pin and leave XCOUT pin open. Sub clock output XCOUT O VCC1 BCLK output BCLK O VCC2 Outputs the BCLK signal. Clock output CLKOUT O VCC2 Outputs a clock with the same frequency as fC, f1, f8, or f32. INT interrupt input INT0 to INT2 I VCC1 Input for the INT interrupt. INT3 to INT7 I VCC2 NMI interrupt input NMI I VCC1 Input for the NMI interrupt. Key input interrupt input KI0 to KI3 I VCC1 Input for the key input interrupt. Timer A TA0OUT to TA4OUT I/O VCC1 I/O for timers A0 to A4 (TA0OUT is N-channel open drain output). TA0IN to TA4IN I VCC1 Input for timers A0 to A4. ZP I VCC1 Input for Z-phase. Timer B TB0IN to TB5IN I VCC1 Input for timers B0 to B5. Three-phase motor control timer U, U, V, V, W, W O VCC1 Output for the three-phase motor control timer. SD I VCC1 Forced cutoff input. IDU, IDV, IDW I VCC2 Input for the position data. Real-time clock output RTCOUT O VCC1 Output for the real-time clock. Timer S INPC1_0 to INPC1_7 I VCC2 Input for the time measurement function. OUTC1_0 to OUTC1_7 O VCC2 Output for the waveform generation function. TSUDA, TSUDB I VCC1 Input for two-phase pulse. Serial interface UART0 to UART5 CTS0 to CTS5 I VCC1 Input pins to control data transmission. RTS0 to RTS5 O VCC1 Output pins to control data reception. CLK0 to CLK5 I/O VCC1 Transmit/receive clock I/O. RXD0 to RXD5 I VCC1 Serial data input. TXD0 to TXD5 O VCC1 Serial data output. (2) CLKS1 O VCC1 Output for the transmit/receive clock multiple-pin output function. UART0 to UART5 I2C mode SDA0 to SDA5 I/O VCC1 Serial data I/O.(2) SCL0 to SCL5 I/O VCC1 Transmit/receive clock I/O.(2) |
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