Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

UPD30121 Datasheet(PDF) 39 Page - NEC

Part # UPD30121
Description  VR4121TM 64-/32-BIT MICROPROCESSOR
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD30121 Datasheet(HTML) 39 Page - NEC

Back Button UPD30121 Datasheet HTML 35Page - NEC UPD30121 Datasheet HTML 36Page - NEC UPD30121 Datasheet HTML 37Page - NEC UPD30121 Datasheet HTML 38Page - NEC UPD30121 Datasheet HTML 39Page - NEC UPD30121 Datasheet HTML 40Page - NEC UPD30121 Datasheet HTML 41Page - NEC UPD30121 Datasheet HTML 42Page - NEC UPD30121 Datasheet HTML 43Page - NEC Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 76 page
background image
Data Sheet U14691EJ1V0DS00
39
µµµµPD30121
(5)
EDO-type DRAM read parameter (1/2)
The target DRAM is the
µPD42S16165L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60,
42S65165G5-A50, or 42S65165G5-A60.
Parameter
Symbol
Condition
MIN.
MAX.
Unit
MRAS (0:3)# pulse width
tRASP
70
ns
MRAS (0:3)# hold time (from UCAS#/LCAS# precharge)
tRHCP
45
ns
MRAS (0:3)# precharge time
tRP
43
ns
UCAS#/LCAS# hold time (from MRAS (0:3)#)
tCSH
50
ns
UCAS#/LCAS# pulse width
tHCAS
10
ns
UCAS#/LCAS# precharge time
tCP
10
ns
Read/write cycle time
tHPC
25
ns
MRAS (0:3)# hold time (from UCAS#/LCAS#)
tRSH
25
ns
Row address setup time (to MRAS (0:3)#)
tASR
0ns
UCAS#/LCAS#
↓ delay time from MRAS (0:3)# ↓
tRCD
24
ns
Column address delay time from MRAS (0:3)#
↓
tRAD
22
ns
Column address setup time (to UCAS#/LCAS#)
tASC
0ns
Column address read time (to MRAS (0:3)#
↑)tRAL
40
ns
Row address hold time (from MRAS (0:3)#
↓)tRAH
20
ns
Column address hold time 1 (from UCAS#/LCAS#
↓)tCAH1
10
ns
Column address hold time 2 (from UCAS#/LCAS#
↓)tCAH2
10
ns
Column address hold time 3 (from UCAS#/LCAS#
↓)tCAH3
10
ns
Data access time (from UCAS#/LCAS# precharge)
tACP
39
ns
Data access time (from RD#
↓)tOEA
25
ns
Data input setup time 1 (to UCAS#/LCAS#
↓)tDS1
0ns
Data input hold time 1 (from MRAS (0:3)#)
tDH1
5ns
Data input setup time 2 (to UCAS#/LCAS#
↓)tDS2
0ns
Data input hold time 2 (from MRAS (0:3)#)
tDH2
5ns
Data access time (from MRAS (0:3)#
↓)tRAC
70
ns
Data access time (from column address)
tAA
30
ns
Data access time (from UCAS#/LCAS#
↓)tCAC
20
ns
Caution These ratings are applied only when a device operates within the recommended operating
condition range and the operating ambient temperature is kept constant.
If the power supply voltage or operating ambient temperature changes during DRAM access, the
above ratings are not applied.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com