UPD30121 datasheet(9/76 Pages) NEC

9 / 76 page

Data Sheet U14691EJ1V0DS00

µµµµPD30121

(2/3)

Signal

I/O

Function

ULCAS#/

MRAS2#

This function differs depending on how the DBUS32 signal is set and type of memory being accessed.

When accessing DRAM (EDO type): This signal is active (ULCAS#) when a valid column address is

output via the ADD bus during access of DATA (16:23) signal in the 32-bit data bus.

When accessing SRAM: This is the I/O buffer control signal (ULDQM#) that is used during access of

DATA (16:23) signal in the 32-bit data bus.

During 32-bit access of LCD/high-speed system memory: Byte enable signal that is used during

access of DATA (16:23) signal.

When accessing DRAM (EDO type): This is the DRAM's RAS signal (MRAS2#). This signal is

active when a valid row address is output via the ADD bus for the DRAM connected to the next

highest address after the highest high-order address.

When accessing SDRAM: This is the SDRAM's chip select signal (CS2#). This signal is active when

a command is issued for the SDRAM connected to the second highest high-order address.

MRAS (0:1)#

This function differs depending on the type of memory being accessed.

This is the DRAM's RAS-only signal.

This is the SDRAM's chip select signal (CS (0:1)#).

UCAS#

This function differs depending on the type of memory being accessed.

This is the DRAM's CAS signal. This signal is active when a valid column address is output via the

ADD bus during access of DATA (8:15) signal in the DRAM.

This is the I/O buffer control signal (UDQM#) that is used during access of DATA (8:15) signal.

< During 32-bit access of LCD/high-speed system memory >

This is the byte enable signal that is used during access of DATA (8:15) signal. This signal is active

when a valid address is output via the ADD bus for access to DATA (8:15) signal when the size of

the access bus to the LCD is 32 bits.

LCAS#

This function differs depending on the type of memory being accessed.

This is the DRAM's CAS signal. This signal is active when a valid column address is output via the

ADD bus during access of DATA (0:7) signal in the DRAM.

This is the I/O buffer control signal (LDQM#) that is used during access of DATA (0:7) signal.

< During 32-bit access of LCD/high-speed system memory >

This is the byte enable signal that is used during access of DATA (0:7) signal.

BUSCLK

This is the system bus clock. It is used to output the clock that is supplied to the controller on the

system bus. Its frequency is determined based on the status of the CLKSEL (0:2) signal. Ordinarily,

the frequency is 1/4 of the TClock frequency. (See (5) RS-232C interface signals). The frequency

can be changed via the PMU register settings.

SHB#

This is the system bus high-byte enable signal. During 16-bit system bus access, this signal is active

when the high-order byte is valid on the data bus.

IOR#

This is the system bus I/O read signal. It is active when the VR4121 accesses the system bus to read

data from an I/O port.

IOW#

This is the system bus I/O write signal. It is active when the VR4121 accesses the system bus to write

data to an I/O port.

MEMR#

This is the system bus memory read signal. It is active when the VR4121 accesses the system bus to

read data from memory.

MEMW#

This is the system bus memory write signal. It is active when the VR4121 accesses the system bus to

write data to memory.

ZWS#

This is the system bus zero wait state signal. Set this signal as active to enable the controller on the

system bus to be accessed by the VR4121 without a wait interval.

UPD30121 Datasheet(PDF) 9 Page - NEC

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