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UPD30121 Datasheet(PDF) 60 Page - NEC |
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UPD30121 Datasheet(HTML) 60 Page - NEC |
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60 / 76 page ![]() Data Sheet U14691EJ1V0DS00 60 µµµµPD30121 (16) LCD interface parameter (1/2) Parameter Symbol Condition MIN. MAX. Unit Address setup time (to command signal ↓)Note1 tAS 15 ns Address hold time (from command signal ↑)Note1 tAH 0ns Command signal recovery time Note 1 tRY 30 ns LCDRDY sampling start time tCLR 0ns Command signal delay time from LCDRDY ↑Notes1, 2 tRHCH T × NT × (N + 2) + 29 ns LCDRDY hold time (from command signal ↑)Note1 tRYZ 0ns Data output setup time (to command signal ↑)Notes1, 2 tDVCH T × (N + 2) ns Data output hold time (from command signal ↑)Note1 tCHDV 25 ns Data input setup time (to command signal ↑)Note1 tDS 0ns Data input hold time (from command signal ↑)Note1 tDH 5ns Notes 1. With the VR4121, the RD# and WR# signals are called the command signals for the LCD interface. 2. The values of N is set by using the WLCD/M (0:1) bits of the BCUSPEEDREG register. The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins). CLKSEL2 Signal CLKSEL1 Signal CLKSEL0 Signal T (ns) WLCD/M1 Bit WLCD/M0 Bit N (TClock) 11 1 RFU 008 11 0 35 016 10 1 33 104 10 0 30 112 01 1 33 01 0 30 00 1 33 00 0 38 Remarks 1. Do not set CLKSEL (2:0) signal = 111. 2. Do not set CLKSEL (2:0) signal = 110, 101 with 131 MHz model. |
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