UPD30121 datasheet(10/76 Pages) NEC

10 / 76 page

Data Sheet U14691EJ1V0DS00

µµµµPD30121

(3/3)

Signal

I/O

Function

RSTOUT

This is the system bus reset signal. It is active when the VR4121 resets the system bus controller

(during bus timeout, manipulation of BCUCNTREG1 register, and power-down mode).

MEMCS16#

This is a dynamic bus sizing request signal. Set this signal as active when system bus memory

accesses data in 16-bit width. This signal is invalid when 32-bit width is selected using LCD/high-speed

system bus.

IOCS16#

This is a dynamic bus sizing request signal. Set this signal as active when system bus I/O accesses

data in 16-bit width. This signal is invalid when 32-bit width is selected using LCD/high-speed system

bus.

IOCHRDY

This is the system bus ready signal. Set this signal as active when the system bus controller is ready to

be accessed by the VR4121.

HLDRQ#

This is a hold request signal for the system bus and DRAM bus that is sent from an external bus master.

HLDACK#

This is a hold acknowledge signal for the system bus and DRAM bus that is sent to an external bus

master.

SRAS#/GPIO4

I/O

This function differs depending on the type of memory being accessed.

This is a general-purpose I/O port.

This is the RAS signal for SDRAM and SROM only.

SCAS#/GPIO5

I/O

This function differs depending on the type of memory being accessed.

This is a general-purpose I/O port.

This is the CAS signal for SDRAM and SROM only.

SYSDIR/GPIO6

I/O

This function differs depending on the type of memory being accessed.

This is a general-purpose I/O port.

This is the direction control signal for the buffer used to reduce the DATA bus's load.

SPOWER/

GPIO7

I/O

This function differs depending on the type of memory being accessed.

This is a general-purpose I/O port.

This is the SDRAM's power supply control signal.

(2)

Clock interface signals

Signal

I/O

Function

RTCX1

This is the 32.768-kHz oscillator’s input pin. It is connected to one side of a crystal resonator.

RTCX2

This is the 32.768-kHz oscillator’s output pin. It is connected to one side of a crystal resonator.

CLKX1

This is the 18.432-MHz oscillator’s input pin. It is connected to one side of a crystal resonator.

CLKX2

This is the 18.432-MHz oscillator’s output pin. It is connected to one side of a crystal resonator.

FIRCLK

This is the 48-MHz clock input pin. Fix this at high level when FIR is not used.

UPD30121 Datasheet(PDF) 10 Page - NEC

UPD30121 Datasheet(HTML) 10 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL