UPD30121 datasheet(8/76 Pages) NEC

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Data Sheet U14691EJ1V0DS00

µµµµPD30121

1. PIN FUNCTIONS

Remark # indicates active low.

1.1 Pin Functions

(1)

System bus interface signals

(1/3)

Signal

I/O

Function

ADD25/SCLK

This function differs depending on how the SMODE (1:2) signal is set.

This is a 25-bit address bus.

<When SMODE (1:2) signal

≠ 00>

This is the operating clock for SDRAM and SROM.

ADD (0:24)

This is a 25-bit address bus.

The VR4121 uses this to specify addresses for the SDRAM, SROM,

DRAM, ROM, LCD, or system bus (ISA).

DATA (0:15)

I/O

This is a 16-bit data bus. The VR4121 uses this to transmit and receive data with a SDRAM, SROM,

DRAM, ROM, LCD, or system bus.

DATA (16:31)/

GPIO (16:31)

I/O

This function differs depending on how the DBUS32 signal is set.

This is the high-order 16 bits of the 32-bit data bus.

This bus is used for transmitting and receiving data between the VR4121 and the DRAM and ROM.

This is a general-purpose I/O port.

LCDCS#

This is the LCD chip select signal. This signal is active when the VR4121 is performing LCD access and

high-speed system bus access using the ADD/DATA bus.

RD#

This is active when the VR4121 is reading data from the LCD, SDRAM, SROM, DRAM, or ROM.

WR#

This is active when the VR4121 is writing data to the LCD, SDRAM, or DRAM.

LCDRDY

This is the LCD ready signal. Set this signal as active when the LCD controller is ready to receive

access from the VR4121.

ROMCS (2:3)#

The function differs with the setting of the DBUS32 signal.

This becomes the chip select signal for the extended ROM, SROM, DRAM, or SDRAM.

This is the ROM or SROM chip select signal.

ROMCS (0:1)#

This is the ROM or SROM chip select signal.

CKE

This is the SDRAM or SROM clock enable signal. When using neither SDRAM nor SROM, connect to

GND or leave open.

UUCAS#/

MRAS3#

This function differs depending on how the DBUS32 signal is set or types of memory to be accessed.

When accessing DRAM (EDO type): This signal is active (UUCAS#) when a valid column address is

output via the ADD bus during access of DATA (24:31) in the 32-bit data bus.

When accessing SDRAM: This is the I/O buffer control signal (UUDQM#) that is used during access

of DATA (24:31) signal in the 32 bit data bus.

During 32-bit access of LCD/high-speed system memory: Byte enable signal that is used during

access of DATA (24:31) signal.

When accessing DRAM (EDO type): This is the DRAM's RAS signal (MRAS3#). This signal is

active when a valid row address is output via the ADD bus for the DRAM connected to the high-order

address.

When accessing SDRAM: This is the SDRAM's chip select signal (CS3#). This signal is active when

a command is issued for the SDRAM connected to the high-order address.

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