UPD30121 datasheet(17/76 Pages) NEC

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Data Sheet U14691EJ1V0DS00

µµµµPD30121

1.2 Pin Status in Specific Status

(1/4)

Pin Name

After Reset by

the RTC Reset

After Reset by the

Deadman’s Switch

or RSTSW# Signal

In the Suspend

Mode

In the Hibernate

Mode or Shut Down

by the HAL Timer

During a Bus

Hold

ADD25/SCLK

Note 1

Note 2

0Hi-Z

ADD (0:24)

Note 2

0Hi-Z

DATA (0:15)

Note 2

0Hi-Z

DATA (16:31)/

GPIO (16:31)

Hi-Z

Note 2

Hi-Z

Hi-Z/

Note 2

LCDCS#

Hi-Z

RD#

Hi-Z

WR#

Hi-Z

LCDRDY

−−

−

ROMCS (2:3)#

Hi-Z

Note 3

ROMCS (0:1)#

Hi-Z

UUCAS#/MRAS3#

Note 4

Note 5

Note 6

0Hi-Z

ULCAS#/MRAS2#

Note 4

Note 5

Note 6

0Hi-Z

MRAS (0:1)#

Hi-Z

UCAS#

Note 7

Hi-Z

LCAS#

Note 7

Hi-Z

BUSCLK

Note 2

Note 8

Notes 1. This differs depending on the setting of the SCLK bit in the SDRAMMODEREG register.

When SCLK bit has a value of "1": outputs clock.

When SCLK bit has a value of "0": low level is output.

2. Maintains the state of the previous Full-speed Mode.

3. When used as the chip select for the ROM or extended ROM, this is the same as ROMCS (0:1)# pins.

When used as the RAS for the extended DRAM, this is the same as MRAS (0:1)# pins.

4. When DBUS32 signal = 1, this becomes the high impedance state.

When DBUS32 signal = 0, the high level is output.

5. When DBUS32 signal = 1: See Note 7 below.

When DBUS32 signal = 0: high level is output.

6. When DBUS32 signal = 1: low level is output.

When DBUS32 signal = 0: high level is output.

7. Reset by the RSTSW# signal: The pin outputs a low level. (Self refresh)

Reset by the Deadman’s switch: The pin outputs a high level.

8. Bus hold from the Suspend Mode: The state of the previous Full-speed Mode is maintained.

Bus hold from Full-speed Mode or Standby Mode: Outputs clocks.

Remark 0: low level, 1: high level, Hi-Z: high impedance

UPD30121 Datasheet(PDF) 17 Page - NEC

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