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UPD78P014 Datasheet(PDF) 33 Page - NEC |
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UPD78P014 Datasheet(HTML) 33 Page - NEC |
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33 / 62 page  33 µPD78P014 Parameter SCK cycle time SCK high-/low-level width SB0, SB1 setup time (to SCK ↑) SB0, SB1 hold time (from SCK ↑) SB0, SB1 output delay time from SCK ↓ SB0, SB1 ↓ from SCK↑ SCK ↓ from SB0, SB1↓ SB0, SB1 high-level width SB0, SB1 low-level width (c) SBI mode (SCK...Internal clock output) MIN. TYP. MAX. Unit 800 ns 3200 ns tKCY3/2 - 50 ns tKCY3/2 - 150 ns 100 ns 300 ns tKCY3/2 ns 0 250 ns 0 1000 ns tKCY3 ns tKCY3 ns tKCY3 ns tKCY3 ns Symbol tKCY3 tKH3 tKL3 tSIK3 tKSI3 tKSO3 tKSB tSBK tSBH tSBL Test Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V R = 1 k Ω, VDD = 4.5 to 6.0 V C = 100 pFNote Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. |
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