LM3754 datasheet(13/47 Pages) TI

13 / 47 page

LM3754

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SNVS789B – JANUARY 2012 – REVISED APRIL 2013

Functional Description

General

The LM3754 is a two-phase voltage-mode step-down (buck) switching regulator controller. From one to six

LM3754 controllers can be connected together to control from two to twelve phases (2, 3, 4, 5, 6, 8, 10, or 12

phases). Since external switching components can typically handle 25A per phase, a 12 phase system can

supply a total of 300A.

Multiple controllers in a system communicate with each other and work together. They will startup and shut down

together, each phase on each controller will share current equally, and all the phases will react in unison to fault

conditions. In a multi-controller system, all controllers are the same part. One controller functions as the Master

and all the others act as Slaves. The Master and Slave are differentiated by how they are connected in the

system. The Master controller senses the system output voltage and VIN (as well as SS) and sets the target duty

cycle for each phase on all of the controllers. The Master and Slave controllers monitor the current-sense

information from each phase. Based on this current information, the controllers adjust the duty cycle on each

phase up or down from the target level, in order to achieve optimal current sharing.

Each controller incorporates a phase locked loop (PLL) that communicates with the PLLs on the other

controllers. By this means, the switching edges of the different phases are spread out equally within one switch

period. For N phases operating at any switching frequency, the angle in degrees between one phase switching

and the next is 360° / N. A SYNC pin is available that can be used to lock the Master switching frequency and

phase to an external clock.

The LM3754 has a Soft-Start function. The Master controller sources 10 µA out of the SS pin so that the output

voltage rise time is controlled by the size of the external SS capacitor. The LM3754 will not pull down a pre-

biased load. The synchronous NFET switch is not turned on during the soft-start cycle until the SS ramp exceeds

either the FB voltage or the internal reference voltage VREF. At this point a gradual transition to synchronous

switching is initiated.

Control Algorithm

The control architecture is primarily voltage-mode. An error amplifier amplifies the difference between the FB pin

voltage and the internal reference voltage to generate a COMP signal. This signal is compared against a ramp

that consists of a fixed value plus a term proportional to VIN which controls the duty cycle. In order to facilitate

current sharing there is an inner current-sense loop. Information for the current through the inductor in each

phase is sensed either with a sense resistor or with a DCR arrangement which uses the DC resistance of the

inductor. This current-sense signal is connected to the CS pin (CS1 or CS2). The negative reference for current-

sense is VOUT which is common for both phases and connected to the controller’s CSM pin. The controller

amplifies the (CS1(2) – CSM) voltage difference for each phase, and compares it to the voltage on the IAVE pin,

which tracks the average current of all phases. Any phase whose current is more than the average has its duty

cycle decreased and vice versa. The IAVE signal is common to all controllers in a system. Each controller

outputs a current onto the IAVE bus so that the total current on the bus is the sum of the current signals from all

of the phases. An external resistor to ground translates this current signal to a voltage, which all of the controllers

read back.

The LM3754 includes an uncommitted differential amplifier. On the Master controller this amplifier is used to

remotely sense the converter’s output voltage, typically at the load. On the Slave controllers this amplifier is used

to buffer the Master controller’s COMP signal and level shift it to the Slave controller’s local ground.

Power Connections

The LM3754 has three supply pins, which are VIN, VCC, and VDD. It employs two ground pins, SGND and

PGND. VDD and PGND are the power and ground for the gate driver stage that controls the HG and LG pins.

The quiescent current drawn by VDD is very small – around 1 mA. To predict the VDD current requirement one

can assume it is mostly switching current and use the standard formula:

IVDD = (1 or 2) x fSW x QTOTAL_PHASE

(1)

QTOTAL_PHASE is the sum of the high-side switch gate charge and the low-side gate charge. The (1 or 2) factor

corresponds to one or two phases running. The low-side driver is powered directly from VDD. The high-side

driver draws its power from VDD through the external bootstrap Schottky diode. The rest of the controller is

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