LM3754 datasheet(2/47 Pages) TI

2 / 47 page

DAP (should be tied to

SGND and PGND on board)

BOOT2

CS1

CSM

ILIM

CS2

IAVE

BOOT1

PGOOD

SYNCOUT

SYNC

NBASE

VIN

VCC

LM3754

WQFN-32

5 x 5 x 0.8 mm body size

0.5 mm pitch

FAULT

LM3754

SNVS789B – JANUARY 2012 – REVISED APRIL 2013

www.ti.com

Connection Diagram

Figure 1. Top View

32-Lead WQFN

Pin Descriptions

Pin Number

Pin Name

Description

HG2

Gate drive of the high-side N-channel MOSFET for Phase 2.

SW2

Switching node of the power stage of Phase 2.

LG2

Gate drive of the low-side N-channel MOSFETs for Phase 2.

VDD

Power supply for gate drivers. Decouple VDD to PGND with a ceramic capacitor. VDD can either be

supplied by an external 5V ±10% bus, or by the internal regulator, which uses an external NPN pass

device. If using the internal regulator, connect VDD to the emitter of the NPN pass device.

PGND

Power Ground. Tie PGND and SGND together on the board through the DAP.

LG1

Gate drive of the low-side N-channel MOSFETs for Phase 1.

SW1

Switching node of the power stage of Phase 1.

HG1

Gate drive of the high-side N-channel MOSFET for Phase 1.

BOOT1

Bootstrap of Phase 1 for the high-side gate drive power supply.

PGOOD

Power Good open-drain output. Active HIGH.

SYNCOUT

Synchronization Output. For multi-controller systems this pin should be connected to the SYNC pin of

the next controller in daisy-chain configuration

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