LM3754 datasheet(19/47 Pages) TI

19 / 47 page

RFRQ =

fSW

40.56 pF

- 142 ns

LM3754

www.ti.com

SNVS789B – JANUARY 2012 – REVISED APRIL 2013

Current Sharing and Current Averaging

The current sharing works by adjusting the duty cycle of each phase up or down to make the phase current

equal to the average current. The maximum duty cycle shift is ±20%.

To determine the average current, each phase sources a current onto the IAVE bus proportional to its load

current as measured by the current sense amplifier connected to the CS1(2) and CSM pins. The IAVE pins of all

controllers are connected together and a resistance of 8 k

Ω per phase (parallel) to SGND provides the proper

voltage level for the IAVE bus. Each phase compares its current sense output to the IAVE bus and sums the

resultant voltage into the common COMP signal to adjust the duty cycle for optimum current sharing.

IAVE forms the current sharing bus for the entire power converter. The IAVE pins of all controllers must be

connected together. Filter capacitors with a time constant of RAV x CAV = 1 / fSW are connected between IAVE

and SGND of each controller. The parallel combination of the filter capacitors times the summing resistors (one

set per controller) forms the time constant of the current sharing bus.

Error Amplifier and Loop Compensation

The LM3754 uses a voltage mode PWM control method. This requires a TYPE III or 3 pole, 2 zero compensation

for optimum bandwidth and stability. The error amplifier is a voltage type operational amplifier with 70 dB open

loop gain and unity gain bandwidth of 15 MHz. This allows for sufficient phase boost at high control loop

frequencies without degrading the error amplifier performance.

The error amplifier output COMP connections are different for Master and Slave controllers. For the Master, a

compensation network is placed between the COMP pin and the FB pin. The COMP pin of the Master is

connected to the SNSP pin of each Slave. The SNSM pin of each Slave is connected to the bottom of the Master

feedback divider at SGND. The COMP pin of each Slave is connected to its corresponding VDIF pin. This

provides sufficient buffering of the master COMP signal for the internal summing of the current averaging circuit.

Oscillator and Synchronization

A resistor and decoupling capacitor are connected between FREQ and SGND to program the switching

frequency between 200 kHz to 1 MHz. These components must be supplied on each controller, even if the

system is synchronized to an external clock.

The switching frequency and synchronization are controlled by the Master. The Master can switch in a free-

running mode or be synchronized to an external clock. To synchronize the Master apply the external clock to the

SYNC pin of the Master, otherwise ground this pin. The amplitude of the signal on the SYNC pin must be limited

to be between 0V and VCC.

The value of the frequency setting resistor is determined as:

(5)

A 1000 pF ceramic capacitor is used to provide sufficient decoupling. If the Master is synchronized set the

resistor according the nominal applied frequency. If the signal on the SYNC pin is below 150 kHz the signal will

be ignored and the device will revert to free-running mode. The SYNCOUT signal from the Master is applied to

the first Slave’s SYNC pin. The SYNCOUT pin of the first Slave is connected to the SYNC pin of the second

Slave, and so on, in a daisy chain configuration. SYNCOUT of the last Slave (or the Master in a single controller

system) is left unconnected.

The configuration of the system, namely the number of controllers and phases is programmed by the voltage on

the PH pin. For each controller connect the midpoint of a resistor divider between VCC and SGND to the PH pin.

The division ratios are given in the Electrical Characteristics table and nominal resistor values in Table 1. This

sets the phase shift between SYNC and the SYNCOUT pin. Where an even number of phases (N) are

employed, the phase delay from SYNC to SYNCOUT is 360°/N. The phase difference between the two phases

on the same controller is 180°. For systems with an odd number of the phases, the HG2 and LG2 gate drivers on

the last Slave are unconnected and the phase arrangement is set according to Table 1

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