LMX2433 datasheet(17/53 Pages) TI1

17 / 53 page

LMX2430, LMX2433, LMX2434

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SNAS187D – FEBRUARY 2003 – REVISED JANUARY 2016

Bench Test Setups (continued)

Figure 28 shows the setup required to measure the RF input impedance of the LMX243x device. The same

setup is used for the LMX2430PW evaluation board. Measuring the input impedance of the device facilitates the

design of appropriate matching networks to match the PLL to the VCO, or in more critical situations, to the

characteristic impedance of the printed-circuit-board (PCB) trace, to prevent undesired transmission line effects.

The FinIF input impedance is evaluated in the same way.

Before the actual measurements are taken, the network analyzer must be calibrated, that is, the error coefficients

must be calculated. The calibration standard of the network analyzer is used to calculate these coefficients. The

calibration standard includes an open, short and a matched load. A 1-port calibration is implemented here.

To calculate the coefficients, the PLL chip is first removed from the PCB. A piece of semi-rigid coaxial cable is

then soldered to the pad on the PCB which is equivalent to the FinRF pin on the PLL chip. Proper grounding

near the exposed tip of the semi-rigid coaxial cable is required for accurate results. The DC blocking capacitor is

removed for this test. The network analyzer port is then connected to the other end of the semi-rigid coaxial

cable. In this way, the semi-rigid coaxial cable acts as a transmission line. This transmission line adds electrical

length and produces an offset from the reference plane of the network analyzer; therefore, it must be included in

the calibration. The desired operating frequency is then set. The typical frequency range selected for the RF

synthesizer of the LMX243x device is from 100 MHz to 6000 MHz.

The network analyzer calculates the calibration coefficients based on the measured S11 parameters. With this all

done, calibration is now complete.

The PLL chip is then placed on the PCB, and a power supply connected to VCC. The EN, ENosc, and OSCin pins

are all tied to VCC. Alternatively, the OSCin pin can be tied to ground. In this setup, the complementary input

(FinRF*) is AC-coupled to ground. With the network analyzer still connected to the semi-rigid coaxial cable, the

measured FinRF impedance is displayed.

The OSCin input impedance is measured in the same way. The impedance is measured when the oscillator

buffer is powered up (ENosc is set HIGH) and when the oscillator buffer is powered down (ENosc pin is set

LOW).

Table 1. LMX243x ULGA FinRF Input Impedance Table(1)

fFinRF

Γ|

ANGLE (

Γ)

Re {ZFinRF}

Im {ZFinRF}

|ZFinRF|

(MHz)

(°)

(

Ω)

(

Ω)

(

Ω)

100

0.86

–8.63

334.27

–339.55

476.48

200

0.86

–10.72

265.44

–313.48

410.77

300

0.85

–13.48

202.09

–281.42

346.46

400

0.84

–17.01

150.76

–245.31

287.93

500

0.83

–21.05

112.18

–212.85

240.60

600

0.82

–25.32

85.96

–185.41

204.37

700

0.82

–29.78

67.32

–162.49

175.88

800

0.81

–34.35

54.27

–143.15

153.09

900

0.80

–39.02

44.76

–127.07

134.72

1000

0.80

–43.83

37.32

–113.62

119.59

1100

0.79

–48.76

31.65

–102.07

106.86

1200

0.79

–53.90

27.30

–91.89

95.86

1300

0.78

–59.07

23.84

–82.83

86.19

1400

0.78

–64.41

21.34

–74.84

77.82

1500

0.77

–70.04

19.20

–67.56

70.24

1600

0.76

–75.84

17.46

–60.88

63.33

1700

0.75

–82.06

16.27

–54.72

57.09

1800

0.73

–88.56

15.36

–48.89

51.25

1900

0.72

–95.19

14.90

–43.34

45.83

2000

0.70

–101.45

14.32

–38.66

41.23

(1)

VCC = EN = 2.5 V, TA = 25°C

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