LMX2433 datasheet(28/53 Pages) TI1

28 / 53 page

LMX2430, LMX2433, LMX2434

SNAS187D – FEBRUARY 2003 – REVISED JANUARY 2016

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Feature Description (continued)

NOTE

The R and N outputs that are routed to the Ftest/LD are R/2 and N/2, respectively. The

internal /2 circuit is used to provide a 50% duty cycle. Refer to MUX[3:0] - Multifunction

Output Select (R3[23:22]:R0[23:22]) for more details on how to route the appropriate

divider output to the Ftest/LD pin.

9.3.9 Fastlock Output

The LMX243x fastlock feature allows a faster loop response time during lock aquisition. The loop response time

(lock time) can be approximately halved if the loop bandwidth is doubled. In order to achieve this, the same gain

/ phase relationship must be maintained when the loop bandwidth is doubled. When the FLoutRF or OSCout/

FLoutIF pins are configured as fastLock outputs, an open-drain device is enabled. The open-drain device

switches in a resistor parallel, and of equal value, to R2 of the external loop filter.

The loop bandwidth is effectively doubled and stability is maintained. Once locked to the correct frequency, the

PLL returns to a steady-state condition. The LMX243x offers two methods to achieve fastlock: manual and

automatic. Manual fastlock is achieved by increasing the charge pump current from 1 mA (RF_CPG/ IF_CPG Bit

= 0) in the steady-state mode, to 4 mA (RF_CPG/ IF_CPG Bit = 1) in fastlock mode. Automatic fastlock is

achieved by programming the time-out counter register (RF_TOC/ IF_TOC) with the appropriate number of

phase comparison cycles that the RF/ IF synthesizer spends in the fastlock state. Refer to R2 Register and R5

9.3.10 Counter Reset

When the RF_RST/ IF_RST bit is enabled, both the feedback divider (RF_N/ IF_N) and reference divider (RF_R/

IF_R) are held at their load point. When the device is programmed to normal operation, both the feedback divider

and reference divider are enabled and resume counting in close alignment to each other. Refer to RF_RST - RF

Synthesizer Counter Reset (R0[21]) and IF_RST - IF Synthesizer Counter Reset (R3[21]) for more details.

9.4 Device Functional Modes

9.4.1 Power Control

The LMX243x device can be asynchronously powered down when the EN pin is set LOW, independent of the

state of the power-down bits.

NOTE

The OSCout/ FLoutIF pin can still be enabled if the ENosc pin is set HIGH, independent of

the state of the EN pin. This capability allows the oscillator buffer to be used as a crystal

oscillator.

When EN is set HIGH, power down is controlled through the MICROWIRE. The power-down word is comprised

of the RF_PD/ IF_PD bit, in conjunction with the RF_CPT/ IF_CPT bit. The power-down control word is used to

set the operating mode of the device. Refer to RF_CPT - RF Synthesizer Charge-Pump Tri-State (R0[20]),

RF_PD - RF Synthesizer Power Down (R1[23]), IF_CPT - IF Synthesizer Charge-Pump Tri-State (R3[20]), and

IF_PD - IF Synthesizer Power Down (R4[23]) for details on how to program the RF or IF power-down bits.

When either synthesizer is powered down, the respective prescaler, phase detector, and charge-pump circuit is

disabled. The CPoutRF/ CPoutIF, FinRF/ FinIF, and FinRF* pins are all forced to a high impedance state. The

reference divider and feedback divider circuits are held at the load point during power down. The oscillator buffer

is disabled when the ENosc pin is set LOW. The OSCin pin is forced to a HIGH state through an approximate

100-k

Ω resistance when this condition exists. When either synthesizer is activated, the respective prescaler,

phase detector, charge-pump circuit, and the oscillator buffer are all powered up. The feedback divider and

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