LMX2433 datasheet(14/53 Pages) TI1

14 / 53 page

LMX2430, LMX2433, LMX2434

SNAS187D – FEBRUARY 2003 – REVISED JANUARY 2016

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Bench Test Setups (continued)

8.1.2.3 Charge-Pump Output Current Variation vs Temperature

(3)

8.1.3 LMX243x FinRF Sensitivity Test Setup

Figure 25. RF Input Sensitivity Test Setup

Figure 25 shows the setup required to measure the RF input sensitivity level of the LMX243x device. The same

setup is used for the LMX2430PW evaluation board. The purpose of this test is to measure the acceptable signal

level to the FinRF input of the PLL chip. Outside the acceptable signal range, the feedback divider begins to

divide incorrectly and miscount the frequency. The FinIF sensitivity is evaluated in the same way.

The setup uses an open-loop configuration. A power supply is connected to Vcc. The IF PLL is powered down

(IF_PD bit = 1). By means of a signal generator, an RF signal is applied to the FinRF pin. The 3-dB pad provides

a 50-

Ω match between the PLL and the signal generator. The EN, ENosc, and OSCin pins are all tied to VCC.

The N value is typically set to 10000 in CodeLoader, that is, RF_B word = 156 and RF_A word = 16 for RF_P bit

= 0 (LMX2434) or RF_P bit = 1 (LMX2430 and LMX2433). The feedback divider output is routed to the Ftest/LD

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LMX2433 Datasheet(PDF) 14 Page - Texas Instruments