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C164CI Datasheet(PDF) 6 Page - Infineon Technologies AG

Part # C164CI
Description  16-bit CMOS Single-Chip Microcontroller
PDF  53 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

C164CI Datasheet(HTML) 6 Page - Infineon Technologies AG

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Semiconductor Group
6
1998-02
C164CI
Pin Definitions and Functions
Symbol
Pin
Number
Input (I)
Output (O)
Function
P5.0 –
P5.7
76 - 79,
2 - 5
I
I
I
Port 5
is
a
8-bit
input-only
port
with
Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 8)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x).
The following pins of Port 5 also serve as timer inputs:
P5.4
T2EUD
GPT1 Timer T2 Ext.Up/Down Ctrl.Input
P5.5
T4EUD
GPT1 Timer T4 Ext.Up/Down Ctrl.Input
P5.6
T2IN
GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
P5.7
T4IN
GPT1 Timer T4 Input for
Count/Gate/Reload/Capture
P3.4,
P3.6,
P3.8 –
P3.13,
P3.15
8,
9,
10 –
15,
16
8
9
10
11
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
O
I/O
O
I/O
O
Port 3
is
a
9-bit
bidirectional
I/O
port. It
is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
The following Port 3 pins also serve for alternate functions:
P3.4
T3EUD
GPT1 Timer T3 Ext.Up/Down Ctrl.Input
P3.6
T3IN
GPT1 Timer T3 Count/Gate Input
P3.8
MRST
SSC Master-Rec./Slave-Transmit I/O
P3.9
MTSR
SSC Master-Transmit/Slave-Rec. O/I
P3.10
TXD0
ASC0 Clock/Data Output (Asyn./Syn.)
P3.11
RXD0
ASC0 Data Input (Asyn.) or I/O (Syn.)
P3.12
BHE
Ext. Memory High Byte Enable Signal,
WRH
Ext. Memory High Byte Write Strobe
P3.13
SCLK
SSC Master Clock Outp./Slave Cl. Inp.
P3.15
CLKOUT
System Clock Output (=CPU Clock)
P4.0 –
P4.3
P4.5 –
P4.6
17 - 19,
22,
23 -
24
17
...
22
23
24
I/O
I/O
I/O
I/O
O
O
...
O
O
O
I
O
O
Port 4
is
a
6-bit
bidirectional
I/O
port. It
is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
P4.0
A16
Least Significant Segment Addr. Line
CS3
Chip Select 3 Output
...
...
...
P4.3
A19
Segment Address Line
CS0
Chip Select 0 Output
P4.5
A20
Segment Address Line,
CAN_RxD CAN Receive Data Input
P4.6
A21
Most Significant Segment Addr. Line,
CAN_TxD CAN Transmit Data Output



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