C164CI datasheet(18/53 Pages) INFINEON

18 / 53 page

Semiconductor Group

1998-02

C164CI

The Capture/Compare Unit CAPCOM6

The CAPCOM6 unit supports generation and control of timing sequences on up to three 16-bit

capture/compare channels plus one 10-bit compare channel.

In compare mode the CAPCOM6 unit provides two output signals per channel which have inverted

polarity and non-overlapping pulse transitions. The compare channel can generate a single PWM

output signal and is further used to modulate the capture/compare output signals.

In capture mode the contents of compare timer 12 is stored in the capture registers upon a signal

transition at pins CCx.

For motor control applications both subunits may generate versatile multichannel PWM signals

which are basically either controlled by compare timer 12 or by a typical hall sensor pattern at the

interrupt inputs (block commutation).

Compare timers 12 (16-bit) and 13 (10-bit) are free running timers which are clocked by the

prescaled CPU clock.

Figure 5

CAPCOM6 Block Diagram

MCB03700

CC Channel 0

CC60

CC61

CC Channel 1

CC Channel 2

CC62

Mode Select Register

CC6MSEL

T12P

Period Register

16-Bit

Compare Timer T12

T12OF

Offset Register

Control Register

CTCON

Compare Timer T13

10-Bit

T13P

Period Register

CMP13

Compare Register

Trap Register

Control

CC6M CON.H

Commutation

Block

CTRAP

CC60

COUT60

CC61

COUT61

CC62

COUT62

COUT63

CC6POS0

CC6POS1

CC6POS2

CPU

These Registers are not direct accessable. The period and offset registers are loading

a value into the timer registers.

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