C164CI datasheet(9/53 Pages) INFINEON

9 / 53 page

Semiconductor Group

1998-02

C164CI

1) The following behaviour differences must be observed when the bidirectional reset is active:

Bit BDRSTEN in register SYSCON cannot be changed after EINIT.

After a reset bit BDRSTEN is cleared.

Bit WDTR will always be ’0’, even after a watchdog timer reset.

The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader

may be activated when P0L.4 is low.

Pin RSTIN may only be connected to external reset devices with an open drain output driver.

RSTOUT 70

Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or a

watchdog timer reset. RSTOUT remains low until the EINIT

(end of initialization) instruction is executed.

NMI

Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When

the PWRDN (power down) instruction is executed, the NMI pin

must be low in order to force the C164CI to go into power

down mode. If NMI is high, when PWRDN is executed, the

part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

P8.0 –

P8.3

72 -

...

I/O

...

I/O

Port 8

4-bit

bidirectional

I/O

port. It

is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state.

The following Port 8 pins also serve for alternate functions:

P8.0

CC16IO

CAPCOM2: CC16 Cap.-In/Comp.Out

...

P8.3

CC19IO

CAPCOM2: CC19 Cap.-In/Comp.Out

VAREF

Reference voltage for the A/D converter.

VAGND

Reference ground for the A/D converter.

VDD

7, 21,

40, 53,

Digital Supply Voltage:

+ 3 V / + 5 V during normal operation and idle mode.

≥ 2.5 V during power down mode

VSS

6, 20,

41, 56,

Digital Ground.

Pin Definitions and Functions (cont’d)

Symbol

Number

Input (I)

Output (O)

Function

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