TMDS181I datasheet(28/58 Pages) TI1

28 / 58 page

TMDS181

TMDS DRIVER

TMDS RECEIVER

Zo = RT

AVCC

VCC

TMDS181, TMDS181I

SLASE75A – AUGUST 2015 – REVISED OCTOBER 2015

www.ti.com

Table 3. TX Termination Control

PIN 36

DESCRIPTION

CONFIGURATION

TX_TERM_CTL = H

The transmitter has no termination

TX_TERM_CTL = L

The transmit termination impedance is approximately 75

Ω to 150 Ω to support

HDMI2.0a

TX_TERM_CTL = NC

Automatically selects the impedance

•

DR > 3.4 Gbps – 75

Ω to 150 Ω differential near end termination

•

2 Gbps > DR < 3.4 Gbps – 150

Ω to 300 Ω differential near-end termination

•

DR < 2 Gbps – No termination

8.3.10 TMDS Outputs

A 1% precision resistor, 7.06 k

Ω, is recommended to be connected from VSADJ pin to ground to allow the

differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10

mA current sink capability, which provides a typical 500 mV voltage drop across a 50

Ω termination resistor.

Figure 28. TMDS Driver and Termination Circuit

Referring to Figure 28, if VCC (TMDS181 supply) and AVCC (sink termination supply) are both powered, the

TMDS output signals are high impedance when OE = high. The normal operating condition is that both supplies

are active. Refer to Figure 28, if VCC is on and AVCC is off, the TMDS outputs source a typical 5-mA current

through each termination resistor to ground. A total of 33 mW of power is consumed by the terminations

independent of the OEB logical selection. When AVCC is powered on, normal operation (OE controls output

impedance) is resumed. When the power source of the device is off and the power source to termination is on,

the IO(off) output leakage current specification ensures the leakage current is limited to 45 μA or less. The VOD of

the clock and data lanes can be reduced through I2C. See Table 12 for details. Figure 3 shows the different

output voltages based on the different VSADJ settings.

8.3.11 Pre-Emphasis/De-Emphasis

The TMDS181 provides de-emphasis as a way to compensate for ISI loss between the TMDS181 outputs to a

TMDS receiver. There are two methods to implement this function. When in pin strapping mode the PRE_SEL

pin controls this function. The PRE_SEL pin provides - 2 dB or 0 dB de-emphasis, which allows the output signal

pre-conditioning to offset interconnect losses from the TMDS181 device to the TMDS receiver. De-emphasis is

recommended to be set at 0 dB while connecting to a receiver through short PCB route. When pulled to ground

though a 65 k

Ω resistor - 2 dB can be realized, see Figure 11. When using I2C, reg0Ch[1:0] is used to make

these adjustments.

As there are times that true pre-emphasis may be the best solution there are two ways to accomplish this. If pin

strapping is being used the best method is to reduce the VSADJ resistor value thus increasing the VOD swing

and then pulling the PRE_SEL pin to ground using the 65 k

Ω resistor, see . If using I2C there are two methods to

accomplish this. The first is similar to pin strapping by reducing the VSADJ resistor value and then implementing

- 2 dB de-emphasis. The second method is to set reg0Ch[7:5] = 011 and set reg0Ch[1:0] = 01 which will

accomplish the same pre-emphasis setting, see Figure 30.

Submit Documentation Feedback

Product Folder Links: TMDS181 TMDS181I

TMDS181I Datasheet(PDF) 28 Page - Texas Instruments

TMDS181I Datasheet(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL