TMDS181I datasheet(35/58 Pages) TI1

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TMDS181, TMDS181I

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SLASE75A – AUGUST 2015 – REVISED OCTOBER 2015

Table 6. MISC CONTROL Register Field Descriptions (continued)

ADDRESS

BITS

DEFAULT

DESCRIPTION

ACCESS

0Bh

7:5

3’b000

Reserved

4:3

2'b00

TX_TERM_CTL. Controls termination for HDMI TX.

RWU

00 – No termination (default)

01 – 150

Ω to 300 Ω

10 – Reserved

11 – 75

Ω to 150 Ω

Note: Writes are ignored when I2C_EN/PIN = 0; reflects the value of TX_TERM_CTL

pin.

1'b0

DDC_DR_SEL Defines the DDC output speed for DDC bridge

0 = 100 kbps (default)

1 = 400 kbps

1'b0

TMDS_CLOCK_RATIO_STATUS. This field is updated from snoop of DDC write to

RWU

slave address 0xA8 offset 0x20 bit 1 that occurred on the SDA_SRC/SCL_SRC

interface. When bit 1 of address 0xA8 offset 0x20 in the SCDC register set is written

to a 1’b1, then this field will be set to a 1’b1. When bit 1 of address 0xA8 offset 0x20

is written to a 1’b0, then this field will be set to a 1’b0. This field is reset to default

value whenever HPD_SNK is de-asserted for greater than 2 ms.

0 – TMDS Clock is 1/10 of TMDS bit period (default)

1 – TMDS Clock is 1/40 of TMDS bit period

1'b0

DDC_TRAIN_SETDISABLE; This field indicate the DDC training block function status.

If disabled the device will only work in HDMI1.x or DVI modes.

0 – DDC training enable (default)

1 – DDC training disable

Note: To force TMDS_CLOCK_RATIO_STATUS to 1 this register bit must be set to 1

which will force the 1/40 mode for HDMI2.0

0Ch

7:5

3’b000

VSWING_DATA: Data output swing control

000 – Vsadj set (default)

001 – Increase by 7%

010 – Increase by 14%

011 – Increase by 21%

100 – Decrease by 30%

101 – Decrease by 21%

110 – Decrease by 14%

111 – Decrease by 7%

4:2

3’b000

VSWING_CLK: Clock output swing control: Default is set by Vsadj resistor value and

the value of reg_0Dh[0].

000 – Vsadj (default)

001 – Increase by 7%

010 – Increase by 14%

011 – Increase by 21%

100 – Decrease by 30%

101 – Decrease by 21%

110 – Decrease by 14%

111 – Decrease by 7%

1:0

2’b00

HDMI_TWPST1[1:0]. HDMI de-emphasis FIR post-cursor-1 signed tap weight.

RWU

(Retimer Mode Only)

00 – No de-emphasis (default)

01 – 2 dB de-emphasis

10 – Reserved

11 – Reserved

Note: Reflects value of PRE_SEL pin; Writes are ignored when I2C_EN/PIN = 0

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