TMDS181I datasheet(4/58 Pages) TI1

4 / 58 page

TMDS181, TMDS181I

SLASE75A – AUGUST 2015 – REVISED OCTOBER 2015

www.ti.com

Pin Functions(1)

TYPE(2)

DESCRIPTION

NAME

NO.

VCC

13, 43

3.3 V power supply

VDD

14, 23, 24, 37, 48

1.2 V power supply

7, 19, 41, 30,

GND

Ground

Thermal pad

MAIN LINK INPUT PINS

IN_D2p/n

2, 3

Channel 2 differential input

IN_D1p/n

5, 6

Channel 1 differential input

IN_D0p/n

8, 9

Channel 0 differential input

IN_CLKp/n

11, 12

Clock differential input

MAIN LINK OUTPUT PINS (FAILAFE)

OUT_D2n/p

34, 35

TMDS data 2 differential output

OUT_D1n/p

31, 32

TMDS data 1 differential output

OUT_D0n/p

28, 29

TMDS data 0 differential output

OUT_CLKn/p

25, 26

TMDS data clock differential output

HOT PLUG DETECT PINS

HPD_SRC

Hot plug detect output to source side

HPD_SNK

Hot plug detect input from sink side

AUDIO RETURN CHANNEL AND DDC PINS

SPDIF_IN

SPDIF signal input

I/O

ARC_OUT

Audio return channel output

SDA_SRC

Source side TMDS port bidirectional DDC data line

I/O

SCL_SRC

Source side TMDS port bidirectional DDC clock line

SDA_SNK

Sink side TMDS port bidirectional DDC data line

I/O

SCL_SNK

Sink side TMDS port bidirectional DDC clock line

CONTROL PINS

Operation enable/reset pin

OE = L: Power-down mode

OE = H: Normal operation

Internal weak pull up: Resets device when transitions from H to L

Signal detector circuit enable

SIG_EN = L: Signal detect circuit disabled:

SIG_EN

SIG_EN = H: Signal detect circuit enabled: When no valid clock device enters

standby mode.

Internal weak pull down

De-emphasis control when I2C_EN/PIN = Low.

PRE_SEL = L: –2 dB

PRE_SEL

PRE_SEL = No Connect: 0 dB

3 level

PRE_SEL = H: Reserved

When I2C_EN/PIN = High de-emphasis is controlled through I2C

Input receive equalization pin strap when I2C_EN/PIN = Low

EQ_SEL = L: Fixed EQ at 7.5 dB at 3 GHz

EQ_SEL = No Connect: Adaptive EQ

EQ_SEL/A0

3 level

EQ_SEL = H: Fixed at 14 dB at 3 GHz

When I2C_EN/PIN = High address bit 1

Note: 3 level for pin strap programming but 2 level when I2C address

I2C_EN/PIN = High; puts device into I2C Control Mode

I2C_EN/PIN = Low; puts device into pin strap mode

I2C_EN/PIN

Note: I2C CSR is addressable at all times, but features that can be controlled by pin

strapping can only be changed by I2C when this pin is pulled high

I2C clock signal

SCL_CTL

Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be

changed by I2C

(1)

(H) Logic high (pin strapped to VCC through 65 k

Ω resistor); (L) Logic Low (pin strapped to GND through 65 kΩ resistor); (for mid-level

= No connect)

(2)

G = Ground, I = Input, O = Output, P = Power

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