TMDS181I datasheet(32/58 Pages) TI1

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TMDS181, TMDS181I

SLASE75A – AUGUST 2015 – REVISED OCTOBER 2015

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8.5 Register Maps

8.5.1 Local I2C Overview

The TMDS181 local I2C interface is always enabled, but will only be able to overwrite pin strapped features when

I2C_EN/PIN is high. The SCL_CTL and SDA_CTL terminals are used for I2C clock and data respectively. The

TMDS181 I2C interface conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1

(January 2000), and supports the fast mode transfer up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7-

bit device address for TMDS181 decides by the combination of EQ_SEL/A0 and A1. Figure 31 clarifies the

TMDS181 target address.

Figure 31. TMDS181 I2C Device Address Description

A1/A0

7 (MSB)

0 (W/R)

HEX

0/1

BC/BD

0/1

BA/BB

0/1

B8/B9

0/1

B6/B7

The typical source application of the TMDS181 is as a retimer in a TV connecting the HDMI output connector

and an internal HDMI transmit through flat cables. The register setup can adjust by source side. When TMDS181

is used in a sink side application, it receives data from input connector and transmits to receiver. Local I2C buses

run at 400 kHz supporting fast-mode I2C operation.

The following procedure is used to write to the TMDS181 I2C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TMDS181 7-bit

address and a zero-value W/R bit to indicate a write cycle.

2. The TMDS181 acknowledges the address cycle.

3. The master presents the sub-address (I2C register within TMDS181) to be written, consisting of one byte of

data, MSB-first.

4. The TMDS181 acknowledges the sub-address cycle.

5. The master presents the first byte of data to be written to the I2C register.

6. The TMDS181 acknowledges the byte transfer.

7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the TMDS181.

8. The master terminates the write operation by generating a stop condition (P).

The following procedure is used to read the TMDS181 I2C registers.

1. The master initiates a read operation by generating a start condition (S), followed by the TMDS181 7-bit

address and a one-value W/R bit to indicate a read cycle.

2. The TMDS181 acknowledges the address cycle.

3. The TMDS181 transmits the contents of the memory registers MSB-first starting at register 00h.

4. The TMDS181 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after

each byte transfer; the I2C master acknowledges reception of each data byte transfer.

5. If an ACK is received, the TMDS181 transmits the next byte of data.

6. The master terminates the read operation by generating a stop condition (P).

NOTE

Upon reset, the TMDS181 sub-address is always set to 0x00. When no sub-address is

included in a read operation, the TMDS181 sub-address increments from the previous

acknowledged read or write data byte. If it is required to read from a sub-address that is

different from the TMDS181 internal sub-address, a write operation with only a sub-

address specified is needed before performing the read operation.

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