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WM8993 Datasheet(PDF) 205 Page - Wolfson Microelectronics plc |
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WM8993 Datasheet(HTML) 205 Page - Wolfson Microelectronics plc |
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205 / 229 page ![]() Production Data WM8993 w PD, November 2010, Rev 4.0 205 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R96 (60h) Analogue HP 0 8 HPOUT1_AUT O_PU 1 Enables automatic power-up of HPOUT1 by monitoring HPOUT1L_ENA and HPOUT1R_ENA 0 = Disabled 1 = Enabled 7 HPOUT1L_RM V_SHORT 0 Removes HPOUT1L short 0 = HPOUT1L short enabled 1 = HPOUT1L short removed For normal operation, this bit should be set as the final step of the HPOUT1L Enable sequence. 6 HPOUT1L_OU TP 0 Enables HPOUT1L output stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the DC offset cancellation has been scheduled. 5 HPOUT1L_DL Y 0 Enables HPOUT1L intermediate stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPOUT1L_ENA. 3 HPOUT1R_RM V_SHORT 0 Removes HPOUT1R short 0 = HPOUT1R short enabled 1 = HPOUT1R short removed For normal operation, this bit should be set as the final step of the HPOUT1R Enable sequence. 2 HPOUT1R_OU TP 0 Enables HPOUT1R output stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the DC offset cancellation has been scheduled. 1 HPOUT1R_DL Y 0 Enables HPOUT1R intermediate stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPOUT1R_ENA. Register 60h Analogue HP 0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R98 (62h) EQ1 0 EQ_ENA 0 EQ Enable 0 = EQ disabled 1 = EQ enabled Register 62h EQ1 |
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