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MCP19116 Datasheet(PDF) 48 Page - Microchip Technology

Part # MCP19116
Description  Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller with Improved 8k Word Core
PDF  246 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP19116 Datasheet(HTML) 48 Page - Microchip Technology

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MCP19116/7
DS20005479B-page 48
 2015-2016 Microchip Technology Inc.
6.8
Output Regulation Reference
Voltage Configuration
The VREFCON register controls the error amplifier
reference voltage. This reference is used to set the
current or voltage regulation set point. VREFCON
holds the digital value used by an 8-bit linear DAC,
setting the analog equivalent that gets summed with
the pedestal voltage (VZC) at the non-inverting node of
the error amplifier. VZC is equal to the band gap
voltage (1.23V). The output of the current sense
amplifier A2 is also raised on the pedestal voltage,
effectively canceling its effect on the input. The
pedestal is implemented throughout the analog control
loop to improve accuracy at low levels. The VREF DAC
can be adjusted in 255 steps of 4.8 mV/step.
bit 3-0
SDRVDT<3:0>: SDRV Dead Time Configuration bits (tTD_2)
0000 = 16 ns delay
0001 = 32 ns delay
0010 = 48 ns delay
0011 = 64 ns delay
0100 = 80 ns delay
0101 = 96 ns delay
0110 = 112 ns delay
0111 = 128 ns delay
1000 = 144 ns delay
1001 = 160 ns delay
1010 = 176 ns delay
1011 = 192 ns delay
1100 = 208 ns delay
1101 = 224 ns delay
1110 = 240 ns delay
1111 = 256 ns delay
REGISTER 6-10:
DEADCON: DRIVER DEAD TIME CONTROL REGISTER (CONTINUED)
REGISTER 6-11:
VREFCON: CURRENT/VOLTAGE REGULATION SET POINT CONTROL
REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VREF7
VREF6
VREF5
VREF4
VREF3
VREF2
VREF1
VREF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
VREF<7:0>: Voltage-Controlling Current Regulation Set Point bits
VREF(V) =VBG * N/255 where N is the decimal value written to the VREFCON Register
<VREF7:VREF0> from 0 to 255



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