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MCP19116 Datasheet(PDF) 99 Page - Microchip Technology

Part # MCP19116
Description  Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller with Improved 8k Word Core
PDF  246 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP19116 Datasheet(HTML) 99 Page - Microchip Technology

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 2015-2016 Microchip Technology Inc.
DS20005479B-page 99
MCP19116/7
14.3
Brown-out Reset (BOR)
The BOREN bit <8> in the CONFIG register enables or
disables the BOR mode, as defined in the CONFIG
register. A brown-out occurs when VDD falls below
VBOR for greater than 100 µs minimum. On any Reset
(Power-on, Brown-out, Watchdog Timer, etc.), the chip
will remain in Reset until VDD rises above VBOR (refer
to Figure 14-3). If enabled, the Power-Up Timer will be
invoked by the Reset and will keep the chip in Reset for
an
additional
64 ms.
During
power-up,
it
is
recommended that the BOR configuration bit is
enabled holding the MCU in Reset (OSC turned off and
no code execution) until VDD exceeds the VBOR
threshold. Users have the option of adding an
additional 64 ms delay by clearing the PWRTE bit. At
this time, the VDD voltage level is high enough to
operate the MCU functions only; all other device
functionality is not operational. This is independent of
the value of VIN, which is typically VDD +VDROPOUT.
During power-down with BOR enabled, the MCU
operation will be held in Reset when VDD falls below the
VBOR threshold. With BOR disabled or while operating
in Sleep mode, the POR will hold the part in Reset
when VDD falls below the VPOR threshold.
FIGURE 14-3:
BROWN-OUT SITUATIONS
Note:
The Power-Up Timer is enabled by the
PWRTE bit in the CONFIG register. If VDD
drops below VBOR while the Power-Up
Timer is running, the chip will go back into
a Brown-out Reset and the Power-Up
Timer will be re-initialized. Once the VDD
rises above VBOR, the Power-Up Timer
will execute a 64 ms reset.
VDD
Internal
VDD
VDD
Internal
Internal
VBOR
VBOR
VBOR
64 ms (1)
64 ms (1)
64 ms (1)
<64ms
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
Reset
Reset
Reset



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