MCP19116 datasheet(76/246 Pages) MICROCHIP

76 / 246 page

MCP19116/7

DS20005479B-page 76

 2015-2016 Microchip Technology Inc.

FIGURE 10-3: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

10.5

USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master

mode in the fact that the shift clock is supplied exter-

nally at the GPB6/TX/CK/AN7 pin (instead of being

supplied internally in Master mode). This allows the

device to transfer or receive data while in Sleep mode.

Slave mode is entered by clearing bit CSRC

(TXSTA<7>).

10.5.1

SYNCHRONOUS SLAVE TRANSMIT

MODE

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep

mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following occurs:

The first word immediately transfers to the TSR

The second word remains in TXREG register.

Flag bit TXIF is not set.

When the first word has been shifted out of TSR,

the TXREG register transfers the second word

to the TSR and flag bit TXIF is not set.

If enable bit TXIE is set, the interrupt wakes the

chip from Sleep and if the global interrupt is

enabled, the program branches to the interrupt

vector (0004h).

When setting up a Synchronous Slave Transmission,

follow these steps:

Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

Clear bits CREN and SREN.

If interrupts are desired, then set enable bit

TXIE.

If 9-bit transmission is desired, then set bit TX9.

Enable the transmission by setting enable bit

TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the TXREG

If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

CREN bit

DT pin

CK pin

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

'0'

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7/8

'0'

Q1 Q2 Q3 Q4

RCIDL bit

MCP19116 Datasheet(PDF) 76 Page - Microchip Technology

MCP19116 Datasheet(HTML) 76 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL