MCP19116 datasheet(71/246 Pages) MICROCHIP

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 2015-2016 Microchip Technology Inc.

DS20005479B-page 71

MCP19116/7

FIGURE 10-3:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

10.3.2

ASYNCHRONOUS RECEIVE MODE

The receiver block diagram is shown in Figure 10-4.

The data is received on the GPB7/RX/DT/CCD pin

and drives the data recovery block. The data recovery

block is a shifter operating at x64, x16 or x4 times the

baud rate. The main receive serial shifter operates at

the bit rate or at Fosc. Once asynchronous mode is

selected, reception is enabled by setting the CREN

(RCSTA<4>) bit.

The heart of the receiver is the receive (serial) shift

received data in the RSR is transferred to RCREG (if

empty). If the transfer is complete, flag bit RCIF

(PIR1<6>) is set. The interrupt can be enabled by set-

ting the RCIE (PIE1<6>) bit. Flag bit RCIF is read-only

and cleared by hardware. It is cleared when RCREG

has been read and is empty. RCREG is double buff-

ered (two deep FIFO). It is possible for two bytes of

data to be received and transferred to the RCREG

FIFO and a third byte to begin shifting to the RSR. On

detection of the Stop bit of the third byte, if RCREG is

full, the overrun error bit OERR (RCSTA<1>) will be

set. The word in RSR will be lost. RCREG can be read

twice to retrieve the two bytes in the FIFO. Overrun bit

OERR has to be cleared in software. This is done by

resetting the receive logic (CREN is cleared and then

set). If bit OERR is set, transfers from the RSR register

to RCREG are inhibited, and no further data will be

received. The OERR bit can then be cleared in soft-

ware. Framing error bit FERR (RCSTA<2>) is set if a

Stop bit is detected as clear. The FERR bit and the

ninth receive bit are buffered the same way as the

receive data. Reading the RCREG will load bits RX9D

and FERR with new values. The user will need to read

the RCSTA register before reading RCREG in order to

not lose the old FERR and RX9D data.

The USART module has a special provision for

multi-processor communication. When the RX9 bit is

set in the RCSTA register, nine bits are received and

the ninth bit is placed in the RX9D status bit of the

RSTA register. The port can be programmed such that

when the Stop bit is received, the serial port interrupt

will only activate if the RX9D bit is set. This feature is

enabled by setting the ADDEN bit in the RCSTA regis-

ter and can be used in a multi-processor system as

indicated in this section.

To transmit a block of data in a multi-processor

system, the master processor must first send an

address byte that identifies the target slave. An

address byte is identified by the RX9D bit being a ‘1’

(instead of a ‘0’ for a data byte). If the ADDEN bit is set

in the slave’s RCSTA register, all data bytes will be

ignored. However, if the ninth received bit is equal to a

‘1’, indicating that the received byte is an address, the

slave will be interrupted and the contents of the

Receive Shift Register (RSR) will be transferred into

the receive buffer. This allows the slave to be

interrupted only by addresses, so that the slave can

examine the received byte to see if it is addressed.

The addressed slave will then clear its ADDEN bit and

prepare to receive data bytes from the master.

When the ADDEN bit is set, all data bytes are ignored.

Following the Stop bit, the data will not be loaded into

the receive buffer and no interrupt will occur. If another

byte is shifted into the RSR, the previous data byte will

be lost.

The ADDEN bit will only take affect when the receiver

is configured in 9-bit mode.

To indicate that a reception is in progress, the RCIDL

bit (BAUDCTL<6>) reflects the current state of the

receive operation. This bit is cleared (‘0’) on the lead-

ing edge of a start bit and set (‘1’) upon the end of a

Stop bit. A ‘1’ value in the RCIDL bit signifies that the

receive state machine is idle. The RCIDL bit is

read-only and is valid for both Asynchronous and Syn-

chronous receptions. No interrupt is associated with

the RCIDL bit. See Figures 10-5, 10-6 and 10-7 for

timing details of the RCIDL signal.

Transmit Shift Reg.

Write to TXREG

BRG output

(shift clock)

TX (pin)

TRMT bit

(Transmit shift

WORD 1

WORD 2

WORD 1

WORD 2

Start Bit

Stop Bit

Start Bit

Transmit Shift Reg.

WORD 1

WORD 2

Bit 0

Bit 1

Bit 7/8

Bit 0

Note: This timing diagram shows two consecutive transmissions.

TXIF bit

(Transmit buffer

reg. empty flag)

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