MCP19116 datasheet(97/246 Pages) MICROCHIP

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 2015-2016 Microchip Technology Inc.

DS20005479B-page 97

MCP19116/7

14.0 RESETS

The reset logic is used to place the MCP19116/7 into a

known state. The source of the reset can be

determined by using the device status bits.

There are multiple ways to reset the MCP19116/7

devices:

• Power-on Reset (POR)

• Overtemperature Reset (OT)

•MCLR Reset

•WDT Reset

• Brown-out Reset (BOR)

To allow VDD to stabilize, an optional power-up timer

can be enabled to extend the Reset time after a POR

event.

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset

•MCLR Reset

•MCLR Reset during Sleep

•WDT Reset

• Brown-out Reset

WDT (Watchdog Timer) wake-up does not cause

since wake-up is viewed as the resumption of normal

operation.

TO and PD bits are set or cleared differently in different

Reset situations, as indicated in Table 14-1. The

software can use these bits to determine the nature of

the Reset. Refer to Table 14-2 for a full description of

Reset states of all registers.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 14-1.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. Refer to Section 5.0 “Digital

Electrical

Characteristics”

for

pulse-width

specifications.

FIGURE 14-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

WDT

Module

VDD Rise

Detect

Brown-Out

Reset

Sleep

BOREN

MCLR/TEST_EN

VDD

External

Reset

On-Chip

RC OSC

11-bit Ripple Counter

PWRT

Enable PWRT

Chip_Reset

Power-On Reset

Time-Out

Reset

Brown-Out

Reset

TABLE 14-1:

TIME-OUT IN VARIOUS

SITUATIONS

Power-Up

Wake-Up from

Sleep

PWRTE = 0

PWRTE = 1

TPWRT

——

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