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MCP19116 Datasheet(PDF) 101 Page - Microchip Technology |
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MCP19116 Datasheet(HTML) 101 Page - Microchip Technology |
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101 / 246 page  2015-2016 Microchip Technology Inc. DS20005479B-page 101 MCP19116/7 FIGURE 14-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) 14.7 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Tables 14-3 and 14-4 show the Reset conditions of these registers. VDD MCLR Internal POR PWRT Time-Out OST Time-Out Internal Reset TPWRT TIOSCST VDD MCLR Internal POR PWRT Time-Out OST Time-Out Internal Reset TPWRT TIOSCST TABLE 14-3: RESET STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0x 1 1 Power-on Reset u0 1 1 Brown-out Reset uu 0 u WDT Reset uu 0 0 WDT Wake-Up from Sleep uu 1 0 Interrupt Wake-Up from Sleep uu u u MCLR Reset during normal operation uu 1 0 MCLR Reset during Sleep 0u 0 x Not allowed. TO is set on POR. 0u x 0 Not allowed. PD is set on POR. |
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