MCP19116 datasheet(69/246 Pages) MICROCHIP

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DS20005479B-page 69

MCP19116/7

10.0 ADDRESSABLE USART

MODULE

The Addressable USART module described in this

document is designed into the PIC16F91x.

The features of that module include:

• Asynchronous and Synchronous modes:

- Asynchronous (full duplex)

- Synchronous - Master (half duplex)

- Synchronous - Slave (half duplex)

• 8- and 9-bit data operations

• Single and Continuous Receive modes

• Address detect

• Two-byte FIFOs for Transmit and Receive opera-

tions

• Majority bit detection in Asynchronous mode

• 8-bit Baud Rate generator with speed selection

- Fosc/16 or Fosc/64 for Asynchronous mode

- Fosc/4 for Synchronous mode

• Status bits for

- Framing Error

- Overrun Error

- Transmit Shift Register Status

In addition, the existing USART features are altered.

These features are changed as previous modules did

not exhibit the desired behavior. These alterations

include:

• Holding all USART state machines in Reset while

SPEN (RCSTA<7>) = 0

• Clarification on the TRMT (TXSTA<1>) status bit

10.1

Module Reset

When the SPEN (RCSTA<7>) is cleared, all USART

state machines are held in Reset. This allows for soft-

ware re-initialization of the module by toggling the

SPEN bit. This also causes all status bits to be reset.

All other R/W bits are available to the user, which

allows them to pre-configure the module prior to set-

ting the SPEN bit.

10.2

Pin Placement and Port

Interaction

The bidirectional TX/CK pin is located on GPB6. The

bidirectional RX/DT pin is located on GPB7. If

TRISC<6> and TRISC<7> are configured as inputs

(‘1’), the USART control will automatically reconfigure

the pin from input to output as needed.

10.3

USART Asynchronous mode

this

mode,

the

USART

uses

standard

non-return-to-zero (NRZ) format (one Start bit, eight or

nine data bits, and one Stop bit). The BRG is used to

derive the baud rate frequencies from the system

clock. The USART transmits and receives the LSB

first. The transmitter and receiver are functionally

independent, but use the same data format and baud

rate. The BRG produces a clock, either x4, x16 or x64

of the bit shift rate, depending on its configuration (see

Section 10.3.2, Asynchronous Receive Mode).

Parity is not supported by the hardware, but can be

implemented in software using the ninth data bit

option. Asynchronous mode is stopped during Sleep.

Asynchronous mode is selected by clearing the SYNC

(TXSTA<4>) bit.

10.3.1

ASYNCHRONOUS TRANSMIT

MODE

The USART transmitter block diagram is shown in

Figure 10-1. The heart of the transmitter is the transmit

(serial) shift register (TSR). The shift register obtains

its data from the read/write transmit buffer, TXREG.

The TXREG register is loaded with data via software.

The TSR register is not loaded until the Stop bit has

been transmitted from the previous load. As soon as

the Stop bit is transmitted, TSR is loaded with new

data from the TXREG register (if available). The trans-

mit register (TXREG) is double buffered. As the user

writes to TXREG, the data is transferred from the buf-

fer to the transmit shift register (TSR), thus freeing up

the buffer register.

The interrupt flag TXIF is set as long as the TXEN

(TXSTA<5>) bit is set and TXREG is empty, indicating

that the transmit buffer register (TXREG) is enabled

and free to accept another word. Flag bit TXIF

(Transmit Buffer Empty) is read-only and will be set,

regardless of the state of the TXIE bit, and cannot be

cleared in software. It will be reset only when new data

is loaded into TXREG.

Transmission is enabled by setting the enable bit

TXEN. The actual transmission will not occur until the

TXREG register has been loaded with data and the

BRG has produced a shift clock (Figure 10-2). The

transmission can also be started by first loading

TXREG and then setting the enable bit TXEN.

Normally, when transmission is first started, TSR is

empty. At that point, transfer to TXREG will result in an

immediate transfer to TSR, resulting in an empty

TXREG. A back-to-back transfer is thus possible

(Figure 10-3). Clearing the enable bit TXEN during a

transmission will cause the transmission to be aborted

and will reset the transmitter. As a result, the

GPB6/TX/CK/AN7 pin will revert to hi-impedance.

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