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MCP19116 Datasheet(PDF) 88 Page - Microchip Technology |
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MCP19116 Datasheet(HTML) 88 Page - Microchip Technology |
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88 / 246 page  TABLE 11-4: MCP19116/7 SPECIAL REGISTERS SUMMARY BANK 2 Addr. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets (1) Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 102h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000 103h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 104h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 105h WPUGPA — — WPUA5 — WPUA3 WPUA2 WPUA1 WPUA0 --1- 1111 --u- uuuu 106h WPUGPB WPUB7 WPUB6 WPUB5 WPUB4 — — WPUB1 — 1111 --1- uuuu --u- 107h PE1 PDRVEN SDRVEN PDRVBY SDRVBY — ISPUEN PWMSTR_PEN PWMSTR_SEN 0000 -100 0000 -100 108h MODECON MSC1 MSC0 RFB —MSC2 — — — 001- 0--- 001- 0--- 109h ABECON DIGOEN DSEL2 DSEL1 DSEL0 DRUVSEL — EADIS ANAOEN 0000 0-00 0000 0-00 10Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 10Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF (2) 0000 000x 0000 000u 10Ch — Reserved — — 10Dh — Unimplemented — — 10Eh — Unimplemented — — 10Fh — Unimplemented — — 110h SSPADD ADD<7:0> 0000 0000 0000 0000 111h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 112h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000 113h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 114h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 115h SSPMSK1 MSK<7:0> 1111 1111 1111 1111 116h SSPSTAT SMP CKE D/A PS R/W UA BF —— 117h SSPADD2 ADD2<7:0> 0000 0000 0000 0000 118h SSPMSK2 MSK2<7:0> 1111 1111 1111 1111 119h VRSPCAL — — — VRSPCAL4 VRSPCAL3 VRSPCAL2 VRSPCAL1 VRSPCAL0 ---x xxxx ---u uuuu 11Ah VR2SPCAL — — — VR2SP- CAL4 VR2SP- CAL3 VR2SP- CAL2 VR2SPCAL1 VR2SPCAL0 ---x xxxx ---u uuuu 11Bh SPBRG SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SPBRG0 0000 0000 0000 0000 11Ch RCREG USART Receive Data Register 0000 0000 0000 0000 11Dh TXREG USART Transmit Data Register 0000 0000 0000 0000 11Eh TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 0000 0000 0000 11Fh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000 Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists. |
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