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PC87591L Datasheet(PDF) 317 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 317 Page - National Semiconductor (TI) |
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317 / 437 page  Host Controller Interface Modules (Continued) Revision 1.07 317 www.national.com SIB Control Register (SIBCTRL) This register allows the core to control the SIB controller operation. Location: 00 FCEA16 Type: Varies per bit Bit 76543210 Name Reserved RTCMR CSWR CSRD CSAE Reset 00000000 Bit Type Description 0 R/W CSAE (Core to SIB Access Enabled). 0: Core access to the SIB bus is disabled (default) 1: Core access to the SIB bus is enabled. The device to be accessed is selected by the SIB Device Select register. 1 R/W1S CSRD (Core Read from SIB). Writing 1 to this bit starts a read from the SIB; the read is based on the address and enabled device specified in CRSMAE register. A write of 0 to this bit is ignored. This bit is cleared when the read operation is completed, indicating that the data is ready in IHD register. 2RO CSWR (Core Write to SIB). The bit is set by a write operation to IHD register. It is cleared when the write to the SIB is completed. 3 R/W1S RTCMR (Real-Time Clock (RTC) Master Reset). Writing 1 to this bit generates a reset pulse to the RTC module. This bit is cleared by the hardware once the reset pulse is completed. Writing 0 to this bit is ignored. 7-4 Reserved. |
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