PC87591L datasheet(395/437 Pages) NSC

395 / 437 page

7.0 Device Specifications (Continued)

Revision 1.07

395

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7.6.8

PS/2 Interface Timing

Figure 144. PS/2 Receive Timing

Symbol

Figure

Description

Reference Conditions

Min

Max

Unit

PS/2 Input Timing

tPSDIs

144

Input setup time PSDAT1-3

Before FE PSCLK1-3

tPSDIh

144

Input hold time PSDAT1-3

After RE PSCLK1-3

tPSCLKl

144

PSCLK1-3 low time

At 0.8V (Both Edges)

(n+1)tCLK

1 ns

1. ‘n’ is the number of clock cycles, as programed in the IDB ﬁeld. See “PS/2 Control Register (PSCON)” on

page 130.

tPSCLKh

144

PSCLK1-3 high time

At 2.0V (Both Edges)

(n+1)tCLK

1 ns

PS/2 Output Timing

tPSDOv

145

Output valid time

PSDAT1-4

After FE PSCLK1-4

(n + 6) * tCLK

+142 ns

2. ‘n’ is deﬁned in “PS/2 Control Register (PSCON)” on page 130.

tPSDOh

145

Output hold time PSDAT1-4

After FE PSCLK1-4

tPSCLKa

146

Output active time PSCLK1-4 After RE CLK

tPSCLKia

146

Output inactive time

PSCLK1-4

After RE CLK

PSDAT1-4

PSCLK1-4

tPSDIs

tPSCLKl

tPSDIh

tPSCLKh

PC87591L Datasheet(PDF) 395 Page - National Semiconductor (TI)

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