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PC87591L Datasheet(PDF) 397 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 397 Page - National Semiconductor (TI) |
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397 / 437 page ![]() 7.0 Device Specifications (Continued) Revision 1.07 397 www.national.com tSCLhighi 150 SCL high time After SCL RE 16 * tCLK - tSDAri 147 SDA signal fall time 300 ns tSDAfi 147 SDA signal rise time 1 µs tSDAhi 150 SDA hold time After SCL FE 0 ns tSDAsi 150 SDA setup time Before SCL RE 2 * tCLK - ACB Output Timing tSCLhigho 150 SCL high time After SCL RE K * tCLK − 1 µs - tSCLlowo 150 SCL low time After SCL FE K * tCLK − 1 µs - tBUFo 148 Bus free time between Stop and Start condition tSCLhigho - tCSTOso 148 SCL setup time Before Stop condition tSCLhigho - tCSTRho 148, 149 SCL hold time After Start condition tSCLhigho - tCSTRso 149 SCL setup time Before Start condition tSCLhigho - tDHCso 149 Data high setup time Before SCL RE tSCLhigho − t SDAro - tDLCso 148 Data low setup time Before SCL RE tSCLhigho − t SDAfo - tSCLfo 147 SDA signal fall time 300 ns tSCLro 147 SDA signal rise time See note1 tSDAfo 147 SDA signal fall time 300 ns tSDAro 147 SDA signal rise time See note1 - tSDAho 150 SDA hold time After SCL FE 7 * tCLK − tSCLfo - tSDAvo 150 SDA valid time After SCL FE 7 * tCLK + tSDAro - 1. Depends on the signal’s capacitance and the pull-up value. Must be less than 1 µs. Symbol Figure Description Reference Conditions Min Max Unit |
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