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PC87591L Datasheet(PDF) 406 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 406 Page - National Semiconductor (TI) |
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406 / 437 page  7.0 Device Specifications (Continued) www.national.com 406 Revision 1.07 7.6.15 LCLK and RESET1-2 Figure 166. LCLK Waveform Symbol Parameter Min Max Units tCYC 1 1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational parameters at fre- quencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system as long as the clock edges remain “clean” (monotonic) and the minimum cycle and high and low times are not violated. The clock may only be stopped in a low state. LCLK Cycle Time 30 ns tHIGH LCLK High Time 11 ns tLOW LCLK Low Time 11 ns - LCLK Slew Rate2 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock wavering as shown below. 1 4 V/ns - RESET1-2 Slew Rate3 3. The minimum RESET1-2 slew rate applies only to the rising (de-assertion) edge of the reset signal, and ensures that system noise cannot render an otherwise monotonic signal to appear to bounce in the switching range. 50 mV/ns 0.6 VDD 0.2 VDD 0.5 VDD 0.4 VDD 0.3 VDD 0.4 VDD P-to-P (minimum) tHIGH tLOW tCYC |
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