DA7219 datasheet(49/123 Pages) DIALOG

49 / 123 page

DA7219

Audio codec with Advanced Accessory Detect

Company confidential

Datasheet

Revision 2.1

17-Dec -2015

49 of 123

9.6

Clocking

The internal system clock (SYSCLK) from which all other clocks are derived is always at one of two

possible frequencies:

● 12.288 MHz for SR from the 48 kHz family (8, 12, 16, 24, 32, 48, 96 kHz)

● 11.2896 MHz for SR from the 44.1 kHz family (11.025, 22.05, 44.1, 88.2 kHz).

The DA7219 can run with or without an applied MCLK. If no MCLK is applied, the internal reference

oscillator will clock the device. However when using the DAI an MCLK must be provided and

correctly configured.

The DA7219 contains a phase-locked loop (PLL), which supports a range of clocking modes and

input clock (MCLK) frequencies.

9.6.1

MCLK input

MCLK is the master clock input which must be in the range of 2 to 54 MHz.

MCLK can be applied as a full-amplitude square wave, or as a low-amplitude sine wave if the MCLK

squarer circuit has been enabled. The clock squarer circuit is enabled by writing pll_mclk_sqr_en = 1.

This clock squarer allows a sine wave or other low amplitude clock (down to 300 mVpp) to be applied

to the chip. The MCLK input is AC coupled on chip when using the clock squarer mode.

9.6.1.1

MCLK detection

A clock detection circuit will set bit [0] of pll_srm_status = 1 whenever the applied MCLK frequency is

above the minimum detection frequency of approximately 1 MHz. Whenever this bit is high, the

MCLK signal is selected as the clock input to the PLL.

9.6.2

Audio reference oscillator

For best audio performance, a system clock within the specified range is required. The DA7219

codec has an internal reference oscillator that provides the system clock when there is no valid

MCLK signal.

The reference oscillator is automatically enabled whenever the codec is in ACTIVE mode and the

MCLK frequency is below the minimum frequency of 1 MHz. When the codec enters STANDBY

mode, the oscillator is automatically disabled to save power.

9.6.3

PLL bypass mode

If an MCLK signal at 11.2896/12.288 MHz or 22.5792/24.576 MHz or 45.1584/49.152 MHz is

available, the PLL is not required and should be disabled to save power. PLL bypass mode is

activated by setting pll_mode = 00.

In this mode the PLL is bypassed and an audio frequency clock is applied to the MCLK pin of the

codec. The required clock frequency depends on the sample rate at which the audio DACs and

ADCs are operating. These clock frequencies are summarized in Table 37 for the range of DAC and

ADC sample rates that can be configured using the SR register.

DA7219 Datasheet(PDF) 49 Page - Dialog Semiconductor

DA7219 Datasheet(HTML) 49 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL