DA7219 datasheet(52/123 Pages) DIALOG

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DA7219

Audio codec with Advanced Accessory Detect

Company confidential

Datasheet

Revision 2.1

17-Dec -2015

52 of 123

9.6.6

SRM PLL mode (DAI slave)

SRM mode enables the PLL output clock to be synchronized to the incoming WCLK signal on the

DAI. The SRM PLL mode is enabled by setting pll_mode = 10.

When using the digital audio interface in slave mode with the SRM enabled, removing and re-

applying the DAI interface word clock WCLK may cause the PLL lock to be lost. To re-lock the PLL it

is recommended that you disable the SRM (pll_mode = 00), reset the PLL by re-writing to register

PLL_INTEGER, and then re-enable the SRM (pll_mode = 10) after the DAI WCLK has been

reapplied.

When switching sample rates between 44.1 kHz and 48 kHz (or between the multiples of these

sample rates), SRM must be disabled and then re enabled using register bit pll_mode.

9.7

Reference generation

9.7.1

Voltage references

The audio circuits use supply-derived references of 0.45×VDD (VMID) and 0.9×VDD (DACREF).

There is also bandgap-derived fixed voltage reference of 1.2 V (VREF). All three voltage references

require off-chip decoupling capacitors (see Appendix B.6).

Both VREF and VMID are automatically enabled whenever the device enters ACTIVE mode. They

are automatically disabled when entering STANDBY mode.

The VMID reference comes from a high-resistance voltage divider, which combines with the

decoupling capacitor to create a large RC (resistance-capacitance) time constant. This ensures a

noise-free VMID reference.

To minimise startup time, set vmid_fast_charge = 1. This enables a low resistance path to charge the

decoupling capacitor faster.

Fast charge (vmid_fast_charge) must be disabled after start-up as it will increase the noise on the

VMID reference.

The bandgap reference VREF also takes time to charge its decoupling capacitor, but an internal

timer ensures that no circuit that requires VREF is enabled until VREF has reached 1.2 V.

The DACREF voltage reference is produced from VMID by a times-two buffer so is capable of

charging its decoupling capacitor quickly.

9.7.2

Bias currents

DA7219 has a master bias current generation block that is enabled by default using the bias_en bit.

Master bias current generation is set to ‘On’ by default. Each sub system has its own local current

generation block, which is automatically enabled whenever any of its sub-blocks are enabled.

9.7.3

Voltage levels

9.7.4

IO voltage level

The digital input/output pins can be set to operate in either a high voltage (2.5 to 3.6 V) or low voltage

(1.5 to 2.5 V) range using the io_voltage_level bit. See Table 40.

Table 40: IO voltage level setting

io_voltage_level setting

Digital I/O voltage range (V)

2.5 to 3.6

1.2 to 2.5

DA7219 Datasheet(PDF) 52 Page - Dialog Semiconductor

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