SC16C554 datasheet(16/55 Pages) PHILIPS

16 / 55 page

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data

Rev. 05 — 10 May 2004

16 of 55

9397 750 13132

6.6 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C554/554D monitors the

CTS pin for a remote buffer overﬂow indication and controls the RTS pin for local

buffer overﬂows. Automatic hardware ﬂow control is selected by setting EFR[6] (RTS)

and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating

a ﬂow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the

SC16C554/554D will suspend TX transmissions as soon as the stop bit of the

character in process is shifted out. Transmission is resumed after the CTS input

returns to a logic 0, indicating more data may be sent.

With the Auto RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTS pin will not be forced to a logic 1

(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin

will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level

below the programmed trigger. However, under the above described conditions, the

SC16C554/554D will continue to accept data until the receive FIFO is full.

6.7 Software ﬂow control

When software ﬂow control is enabled, the SC16C554/554D compares one or two

sequential receive data characters with the programmed Xon/Xoff or Xoff1,2

character value(s). If received character(s) match the programmed values, the

SC16C554/554D will halt transmission (TX) as soon as the current character(s) has

completed transmission. When a match occurs, the receive ready (if enabled via Xoff

IER[5]) ﬂags will be set and the interrupt output pin (if receive interrupt is enabled) will

be activated. Following a suspension due to a match of the Xoff characters’ values,

the SC16C554/554D will monitor the receive data stream for a match to the Xon1,2

character value(s). If a match is found, the SC16C554/554D will resume operation

and clear the ﬂags (ISR[4]).

Reset initially sets the contents of the Xon/Xoff 8-bit ﬂow control registers to a logic 0.

Following reset, the user can write any Xon/Xoff value desired for software ﬂow

control. Different conditions can be set to detect Xon/Xoff characters and

suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,

the SC16C554/554D compares two consecutive receive characters with two software

ﬂow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions

accordingly. Under the above described ﬂow control mechanisms, ﬂow control

characters are not placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overﬁlling and ﬂow control needs to be executed,

the SC16C554/554D automatically sends an Xoff message (when enabled) via the

serial TX output to the remote modem. The SC16C554/554D sends the Xoff1,2

Table 6:

Flow control mechanism

Selected trigger level

(characters)

INT pin activation

Negate RTS or

send Xoff

Assert RTS or

send Xon

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