SC16C554 datasheet(27/55 Pages) PHILIPS

27 / 55 page

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data

Rev. 05 — 10 May 2004

27 of 55

9397 750 13132

7.4 Interrupt Status Register (ISR)

The SC16C554/554D provides six levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with six

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged

until the pending interrupt is serviced. Whenever the interrupt status register is read,

the interrupt status is cleared. However, it should be noted that only the current

pending interrupt is cleared by the read. A lower level interrupt may be seen after

re-reading the interrupt status bits. Table 12 “Interrupt source” shows the data values

(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated

with each of these interrupt levels.

Table 12:

Interrupt source

Priority

level

ISR[5]

ISR[4]

ISR[3]

ISR[2]

ISR[1]

ISR[0]

Source of the interrupt

00110LSR (Receiver Line Status

00100

RXRDY (Received Data

Ready)

01100

RXRDY (Receive Data

time-out)

00010

TXRDY (Transmitter

Holding Register Empty)

00000

MSR (Modem Status

10000

RXRDY (Received Xoff

signal) / Special character

00000CTS, RTS change of state

Table 13:

Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is

not being used. They are set to a logic 1 when the FIFOs are

enabled.

Logic 0 or cleared = default condition.

5:4

ISR[5:4]

INT priority bits 4-3. These bits are enabled when EFR[4] is set to

a logic 1. ISR[4] indicates that matching Xoff character(s) have

been detected. ISR[5] indicates that CTS, RTS have been

generated. Note that once set to a logic 1, the ISR[4] bit will stay a

logic 1 until Xon character(s) are received.

Logic 0 or cleared = default condition.

3:1

ISR[3:1]

INT priority bits 2-0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 12).

Logic 0 or cleared = default condition.

ISR[0]

INT status.

Logic 0 = An interrupt is pending and the ISR contents may be

used as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

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