SC16C554 datasheet(25/55 Pages) PHILIPS

25 / 55 page

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data

Rev. 05 — 10 May 2004

25 of 55

9397 750 13132

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive

FIFO trigger levels, and select the DMA mode.

7.3.1

DMA mode

Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or

receive operation, and is similar to the 16C454 mode. Transmit Ready (TXRDY) will

go to a logic 0 whenever an empty transmit space is available in the Transmit Holding

Holding Register (RHR) is loaded with a character.

Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The

transmit interrupt is set when there are one or more FIFO locations empty. The

receive interrupt is set when the receive FIFO ﬁlls to the programmed trigger level.

However, the FIFO continues to ﬁll regardless of the programmed level until the FIFO

is full. RXRDY remains a logic 0 as long as the FIFO ﬁll level is above the

programmed trigger level.

7.3.2

FIFO mode

Table 10:

FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7:6]

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO

equals the programmed trigger level. However, the FIFO will continue to

be loaded until it is full. Refer to Table 11.

5:4

FCR[5:4]

Not used; initialized to logic 0.

FCR[3]

DMA mode select.

Logic 0 = Set DMA mode ‘0’ (normal default condition).

Logic 1 = Set DMA mode ‘1’

Transmit operation in mode ‘0’: When the SC16C554/554D is in the

16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode

(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are

no characters in the transmit FIFO or transmit holding register, the

TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a

logic 1 after the ﬁrst character is loaded into the transmit holding

Receive operation in mode ‘0’: When the SC16C554/554D is in

mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;

FCR[3] = logic 0) and there is at least one character in the receive FIFO,

the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a

logic 1 when there are no more characters in the receiver.

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