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SC16C554 Datasheet(PDF) 38 Page - NXP Semiconductors |
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SC16C554 Datasheet(HTML) 38 Page - NXP Semiconductors |
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38 / 55 page ![]() Philips Semiconductors SC16C554/554D Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder Product data Rev. 05 — 10 May 2004 38 of 55 9397 750 13132 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. [1] Applies to external clock, crystal oscillator max 24 MHz. [2] = 333 ns (for Baudratemax = 1.5 Mbit/s) = 1 µs (for Baudratemax = 460.8 kbit/s) = 4 µs (for Baudrate max = 115.2 kbit/s) [3] When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x1, clock cycle. 10.1 Timing diagrams t32d write cycle delay [3] 25 - 25 - 20 - ns t33s data set-up time 20 - 15 - 15 - ns t33h data hold time 15 - 5 - 5 - ns tRESET Reset pulse width 200 - 40 - 40 - ns N baud rate divisor 1 216 − 11 216 − 11 216 − 1R clk Table 27: AC electrical characteristics…continued Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ± 10%, unless otherwise specified. Symbol Parameter Conditions 2.5 V 3.3 V 5.0 V Unit Min Max Min Max Min Max IOWstrobemax 1 2 Baudrate max () -------------------------------------- = Fig 10. General read timing in 68 mode. 002aaa210 t30s t31h A0–A4 CS R/W D0–D7 t31d t30w t30d t30h t32s |
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