SC16C554 datasheet(30/55 Pages) PHILIPS

30 / 55 page

Philips Semiconductors

SC16C554/554D

Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

Product data

Rev. 05 — 10 May 2004

30 of 55

9397 750 13132

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 18:

Modem Control Register bits description

Bit

Symbol

Description

MCR[7]

Reserved; set to 0.

MCR[6]

IR enable.

Logic 0 = Enable the standard modem receive and transmit

input/output interface (normal default condition).

Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.

While in this mode, the TX/RX output/inputs are routed to the

infrared encoder/decoder. The data input and output levels will

conform to the IrDA infrared interface requirement. As such, while

in this mode, the infrared TX output will be a logic 0 during idle data

conditions.

MCR[5]

Reserved; set to 0.

MCR[4]

Loop-back. Enable the local loop-back mode (diagnostics). In this

mode the transmitter output (TX) and the receiver input (RX), CTS,

DSR, CD, and RI are disconnected from the SC16C554/554D I/O

pins. Internally the modem data and control pins are connected into a

loop-back data conﬁguration (see Figure 8). In this mode, the receiver

and transmitter interrupts remain fully operational. The Modem

Control Interrupts are also operational, but the interrupts’ sources are

switched to the lower four bits of the Modem Control. Interrupts

continue to be controlled by the IER register.

Logic 0 = Disable loop-back mode (normal default condition).

Logic 1 = Enable local loop-back mode (diagnostics).

MCR[3]

OP2, INTx enable. Used to control the modem CD signal in the

loop-back mode.

Logic 0 = Forces INTA-INTD outputs to the 3-State mode during

the 16 mode (normal default condition). In the loop-back mode,

sets OP2 (CD) internally to a logic 1.

Logic 1 = Forces the INTA-INTD outputs to the active mode during

the 16 mode. In the loop-back mode, sets OP2 (CD) internally to a

logic 0.

MCR[2]

OP1. This bit is used in the Loop-back mode only. In the loop-back

mode, this bit is used to write the state of the modem RI interface

signal via OP1.

MCR[1]

RTS

Logic 0 = Force RTS output to a logic 1 (normal default condition).

Logic 1 = Force RTS output to a logic 0.

Automatic RTS may be used for hardware ﬂow control by enabling

EFR[6]. See Table 21.

MCR[0]

DTR

Logic 0 = Force DTR output to a logic 1 (normal default condition).

Logic 1 = Force DTR output to a logic 0.

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