ML7396AB datasheet(118/140 Pages) LAPIS

118 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

118/140

●RX FIFO Access Error

If one of the following conditions is met, RX FIFO access error interrupt (INT[14] group2) will be generated.

● Receiving the 3rd packet when the receiving data remain in both FIFO0 and FIFO1.

● RX data overflow occurs to RX_FIFO (Overrun)

● Read RX_FIFO during no data in the RX_FIFO (Underrun)

When RX FIFO access error interrupt occurs, after RX completion interrupt (INT[18]/[19] group3) is

recognized, issuing PHY reset by [RST_SET:B0 0x01] register or FIFO clear by [INT_SOURCE_GRP1:B0

0x24] register. After that, clearing RX completion interrupt and RX FIFO access error interrupt.

After receiving 2 packets, by setting CLK1_EN ([CLK_SET:B0 0x02(1)] = 0b0, RX FIFO access error can be

avoid.

START

RX setting

[RX_ALARM_LH:B0 0x37]

[RX_ALARM_HL:B0 0x38]

RX_ON issue

[RF_STATUS:B0 0x6C]

Refer to RX flowchart

RX process

(packet mode)

RX FIFO access error notification

INT[14]

[INT_SOURCE_GRP2:B0 0x25]

PHY reset issue

[RST_SET:B0 0x01]

Clear FIFO

[INT_SOURCE_GRP1:B0 0x24]

When interrupt caused by overrun, or

underrun, FIFO clear is possible.

Clear interrupts

INT[18],[20] or INT[19].[21]

[INT_SOURCE_GRP3:B0 0x26]

Clear interrupts

INT[14]

[INT_SOURCE_GRP2:B0 0x25]

END

TRX_OFF issue

[RF_STATUS:B0 0x6C]

Next packet TX?

Yes

ML7396AB Datasheet(PDF) 118 Page - LAPIS Semiconductor Co., Ltd.

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